UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 263

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

The setting methods are described below.
<Change the channel>
<Complete A/D conversion>
<Change the channel>
<Complete A/D conversion>
When used as A/D conversion operation
<1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1.
<2> Select the channel and conversion time using bits 2 to 0 (ADS2 to ADS0) of the analog input channel
<3> Set bit 7 (ADCS) of ADM to 1 to start A/D conversion.
<4> An interrupt request signal (INTAD) is generated.
<5> Transfer the A/D conversion data to the A/D conversion result register (ADCR).
<6> Change the channel using bits 2 to 0 (ADS2 to ADS0) of ADS to start A/D conversion.
<7> An interrupt request signal (INTAD) is generated.
<8> Transfer the A/D conversion data to the A/D conversion result register (ADCR).
<9> Clear ADCS to 0.
<10> Clear ADCE to 0.
Cautions 1. Make sure the period of <1> to <3> is 14 s or more.
When used as power-fail function
<1> Set bit 7 (PFEN) of the power-fail comparison mode register (PFM).
<2> Set power-fail comparison condition using bit 6 (PFCM) of PFM.
<3> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1.
<4> Select the channel and conversion time using bits 2 to 0 (ADS2 to ADS0) of the analog input channel
<5> Set a threshold value to the power-fail comparison threshold register (PFT).
<6> Set bit 7 (ADCS) of ADM to 1.
<7> Transfer the A/D conversion data to the A/D conversion result register (ADCR).
<8> The higher 8 bits of ADCR and PFT are compared and an interrupt request signal (INTAD) is generated
<9> Change the channel using bits 2 to 0 (ADS2 to ADS0) of ADS.
<10> Transfer the A/D conversion data to the A/D conversion result register (ADCR).
<11> The higher 8 bits of ADCR and the power-fail comparison threshold register (PFT) are compared and an
<12> Clear ADCS to 0.
<13> Clear ADCE to 0.
Cautions 1. Make sure the period of <3> to <6> is 14 s or more.
specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM.
specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM.
if the conditions match.
interrupt request signal (INTAD) is generated if the conditions match.
2. It is no problem if the order of <1> and <2> is reversed.
3. <1> can be omitted. However, do not use the first conversion result after <3> in this
4. The period from <4> to <7> differs from the conversion time set using bits 5 to 3 (FR2 to
2. It is no problem if the order of <3>, <4>, and <5> is changed.
3. <3> must not be omitted if the power-fail function is used.
4. The period from <7> to <11> differs from the conversion time set using bits 5 to 3 (FR2 to
case.
FR0) of ADM. The period from <6> to <7> is the conversion time set using FR2 to FR0.
FR0) of ADM. The period from <9> to <11> is the conversion time set using FR2 to FR0.
CHAPTER 12 A/D CONVERTER
User’s Manual U16899EJ3V0UD
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