UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 547

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

16-bit
timer/
event
counters
00, 01
(TM00,
TM01)
Function
OVF0n flag
operation
Conflict
operation
Timer operation
Capture
operation
Compare
operation
Edge detection
Details of
Function
The OVF0n flag is also set to 1 in the following case.
When any of the following modes is selected: the mode in which clear & start
occurs on a match between TM0n and CR00n, the mode in which clear & start
occurs at the TI00n valid edge, or the free-running mode
Even if the OVF0n flag is cleared before the next count clock is counted (before
TM0n becomes 0001H) after the occurrence of TM0n overflow, the OVF0n flag is
re-set newly so this clear is not valid.
When a read period of the 16-bit timer capture/compare register (CR00n/CR01n)
and a capture trigger input (CR00n/CR01n used as capture register) conflict, the
priority is given to the capture trigger input. The data read from CR00n/CR01n is
undefined.
Even if 16-bit timer counter 0n (TM0n) is read, the value is not captured by 16-bit
timer capture/compare register 01n (CR01n).
Regardless of the CPU’s operation mode, when the timer stops, the input signals
to the TI00n/TI01n pins are not acknowledged.
The one-shot pulse output mode operates correctly only in the free-running mode
and the mode in which clear & start occurs at the TI00n valid edge. In the mode
in which clear & start occurs on a match between the TM0n register and CR00n
register, one-shot pulse output is not possible because an overflow does not
occur.
If the TI00n pin valid edge is specified as the count clock, a capture operation by
the capture register specified as the trigger for the TI00n pin is not possible.
To ensure the reliability of the capture operation, the capture trigger requires a
pulse longer than two cycles of the count clock selected by prescaler mode
register 0n (PRM0n).
The capture operation is performed at the falling edge of the count clock. An
interrupt request input (INTTM00n/INTTM01n), however, is generated at the rise
of the next count clock.
A capture operation may not be performed for CR00n/CR01n set in compare
mode even if a capture trigger has been input.
If the TI00n or TI01n pin is high level immediately after system reset and the
rising edge or both the rising and falling edges are specified as the valid edge of
the TI00n or TI01n pin to enable the 16-bit timer counter 0n (TM0n) operation, a
rising edge is detected immediately after the operation is enabled. Be careful
therefore when pulling up the TI00n or TI01n pin. However, if the TI00n or TI01n
pin is high level when re-enabling operation after the operation has been stopped,
the rising edge is not detected.
The sampling clock used to remove noise differs when the TI00n pin valid edge is
used as the count clock and when it is used as a capture trigger. In the former
case, the count clock is f
prescaler mode register 0n (PRM0n). The capture operation is started only after
a valid edge is detected twice by sampling, thus eliminating noise with a short
pulse width.
CR00n is set to FFFFH
TM0n is counted up from FFFFH to 0000H.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16899EJ3V0UD
X
, and in the latter case the count clock is selected by
Cautions
p. 179
p. 179
p. 179
p. 180
p. 180
p. 180
p. 180
p. 180
p. 180
p. 180
p. 180
p. 180
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