UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 565

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

E.1 Major Revisions in This Edition
Throughout
p. 17
p. 18
p. 30
p. 31
p. 47
p. 48
p. 49
p. 50
p. 51
p. 52
p. 60
p. 113
p. 114
p. 130
p. 248
p. 264
p. 269
p. 272
p. 274
p. 406
p. 412
p. 420
p. 449
p. 462
p. 463
p. 479
p. 495
p. 515
Page
( PD78F0138HD)
and High-Speed System Clock
Selection Register (LVIS)
Addition of product name, specification, and classification by case on (A) grade products and (A1) grade
products
Deletion of description regarding 64-pin plastic FBGA (8
Modification of Note and Caution in serial operation mode register (CSIM10) and serial clock selection register
(CSIC10)
Addition of Note 2 to 1.1 Features
Modification of 1.3 Ordering Information
Addition of Note 3 to 1.7 Outline of Functions (1/2)
Addition of Note 3 to 1.7 Outline of Functions (2/2)
Modification of Figure 3-1. Memory Map ( PD78F0132H)
Modification of Figure 3-2. Memory Map ( PD78F0133H)
Modification of Figure 3-3. Memory Map ( PD78F0134H)
Modification of Figure 3-4. Memory Map ( PD78F0136H)
Modification of Figure 3-5. Memory Map ( PD78F0138H)
Modification of Figure 3-6. Memory Map ( PD78F0138HD)
Modification of Notes 1 and 2 in Figure 3-12. Correspondence Between Data Memory and Addressing
Addition of Note 5 to Figure 5-2. Format of Processor Clock Control Register (PCC)
Addition of Note 2 to Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution
Time
Addition of Note to Table 5-5. Maximum Time Required to Switch Between Internal Oscillation Clock
Modification of Figure 12-2. Circuit Configuration of Series Resistor String
Modification of description in 12.6 (1) Operating current in standby mode
Addition of Caution 4 to 13.1 (2) Asynchronous serial interface (UART) mode
Addition of Caution 2 to 13.2 (3) Transmit shift register 0 (TXS0)
Addition of Caution 5 to Figure 13-2. Format of Asynchronous Serial Interface Operation Mode Register
0 (ASIM0)
Addition of Caution 3 to 22.1 Functions of Power-on-Clear Circuit
Modification of Note and addition of Caution 2 in Figure 23-3. Format of Low-Voltage Detection Level
Revision of CHAPTER 24 OPTION BYTE
Modification of Table 26-8. Communication Modes
Modification of Notes 1 and 2 in Figure 26-23. Memory Map and Boot Area (6) PD78F0138HD
Revision of CHAPTER 27 ON-CHIP DEBUG FUNCTION ( PD78F0138HD ONLY)
Addition of ”Storage temperature (In flash memory blank state)” to Absolute Maximum Ratings in CHAPTER
29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)
Addition of CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)
Revision of CHAPTER 32 RECOMMENDED SOLDERING CONDITIONS
APPENDIX E REVISION HISTORY
User’s Manual U16899EJ3V0UD
Description
8)
563