UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 187

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

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7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51
(1) Timer clock selection register 5n (TCL5n)
The following four registers are used to control 8-bit timer/event counters 50 and 51.
Note Be sure to set the count clock so that the following condition is satisfied.
Cautions 1. When the internal oscillation clock is selected as the clock to be supplied to the CPU, the
Remarks 1. f
This register sets the count clock of 8-bit timer/event counter 5n and the valid edge of the TI5n pin input.
TCL5n can be set by an 8-bit memory manipulation instruction.
RESET input clears TCL5n to 00H.
Remark n = 0, 1
Address: FF6AH
Symbol
TCL50
Timer clock selection register 5n (TCL5n)
8-bit timer mode control register 5n (TMC5n)
Port mode register 1 (PM1) or port mode register 3 (PM3)
Port register 1 (P1) or port register 3 (P3)
V
V
V
V
2. Figures in parentheses apply to operation at f
DD
DD
DD
DD
2. When rewriting TCL50 to other data, stop the timer operation beforehand.
3. Be sure to clear bits 3 to 7 to 0.
= 4.0 to 5.5 V: Count clock
= 3.3 to 4.0 V: Count clock
= 2.7 to 3.3 V: Count clock
= 2.5 to 2.7 V: Count clock
X
clock of the internal oscillator is divided and supplied as the count clock. If the count clock
is the internal oscillation clock, the operation of 8-bit timer/event counter 50 is not
guaranteed.
: High-speed system clock oscillation frequency
TCL502
7
0
0
0
0
0
1
1
1
1
After reset: 00H
Figure 7-5. Format of Timer Clock Selection Register 50 (TCL50)
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
TCL501
6
0
0
0
1
1
0
0
1
1
R/W
TCL500
10 MHz
8.38 MHz
5 MHz
2.5 MHz (standard products, (A) grade products only)
User’s Manual U16899EJ3V0UD
5
0
0
1
0
1
0
1
0
1
TI50 pin falling edge
TI50 pin rising edge
f
f
f
f
f
f
X
X
X
X
X
X
/2 (5 MHz)
/2
/2
/2
/2
(10 MHz)
2
6
8
13
(2.5 MHz)
(156.25 kHz)
(39.06 kHz)
4
0
(1.22 kHz)
X
= 10 MHz.
3
0
Count clock selection
TCL502
2
Note
TCL501
1
TCL500
0
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