UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 134

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UPD78F0138HGK-9ET-A

Manufacturer Part Number
UPD78F0138HGK-9ET-A
Description
MCU 8BIT 60K FLASH 64TQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx1+r
Datasheet

Specifications of UPD78F0138HGK-9ET-A

Core Processor
78K/0
Core Size
8-Bit
Speed
16MHz
Connectivity
3-Wire SIO, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
42
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
5.8 Clock Switching Flowchart and Register Setting
5.8.1 Switching from internal oscillation clock to high-speed system clock
132
Internal oscillation
High-speed system
Note Check the oscillation stabilization wait time of the high-speed system clock oscillator after reset release
clock operation
clock operation
Register value
after reset
Figure 5-14. Switching from internal oscillation Clock to High-Speed System Clock (Flowchart)
using the OSTC register and then switch to the high-speed system clock operation after the oscillation
stabilization wait time has elapsed. The OSTS register setting is valid only after STOP mode is released by
interrupt during high-speed system clock operation.
High-speed system clock
Internal oscillation
(dividing set PCC)
oscillation stabilization
clock operation
time has not elapsed
High-speed system clock operation
CHAPTER 5 CLOCK GENERATOR
User’s Manual U16899EJ3V0UD
Each processing
OSTS = 05H
OSTC check
OSTC = 00H
RCM = 00H
MCM = 00H
MOC = 00H
PCC setting
MCM.0
PCC = 00H
After reset
High-speed system clock oscillation stabilization time has elapsed
1
Note
Note
; f
; Internal oscillator oscillation
; Internal oscillation clock operation
; High-speed system clock oscillation
; Oscillation stabilization time status register
; Oscillation stabilization time f
CPU
; High-speed system clock oscillation
stabilization time status check
MCM.1 (MCS) is changed from 0 to 1
= f
R
XP
/2
16

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