UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 115

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

<R>
Notes 1.
Caution Be sure to clear bit 3 to 0.
Address: FFFBH
Symbol
PCC
2.
3.
4.
5.
Bit 5 is read-only.
When the CPU is operating on the subsystem clock, MCC should be used to stop the high-speed
system clock oscillator operation. When the CPU is operating on the internal oscillation clock, use bit 7
(MSTOP) of the main OSC control register (MOC) to stop the high-speed system clock oscillator
operation (this cannot be set by MCC). A STOP instruction should not be used.
Clear this bit to 0 when the subsystem clock is used, and set it to 1 when the subsystem clock is not
used.
Be sure to switch CSS from 1 to 0 when bits 1 (MCS) and 0 (MCM0) of the main clock mode register
(MCM) are 1.
Setting is prohibited for the (A1) grade products.
CSS
MCC
MCC
FRC
CLS
<7>
0
1
0
1
0
1
0
1
Note 4
After reset: 00H
Figure 5-2. Format of Processor Clock Control Register (PCC)
Oscillation possible
Oscillation stopped
On-chip feedback resistor used
On-chip feedback resistor not used
High-speed system clock or internal oscillation clock
Subsystem clock
PCC2
FRC
<6>
Other than above
0
0
0
0
1
0
0
0
0
1
R/W
CHAPTER 5 CLOCK GENERATOR
PCC1
Control of high-speed system clock oscillator operation
CLS
Note 1
<5>
User’s Manual U16899EJ3V0UD
0
0
1
1
0
0
0
1
1
0
Subsystem clock feedback resistor selection
PCC0
CSS
<4>
0
1
0
1
0
0
1
0
1
0
CPU clock status
f
f
f
f
f
f
Setting prohibited
X
X
X
X
X
XT
/2
/2
/2
/2
/2
2
3
4
3
0
CPU clock (f
PCC2
f
f
Setting prohibited f
Setting prohibited f
Setting prohibited f
2
R
R
/2
MCM0 = 0
Note 5
Note 3
CPU
) selection
PCC1
Note 2
1
f
f
XP
XP
XP
XP
XP
/2
/2
/2
/2
MCM0 = 1
2
3
4
PCC0
0
113