UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 347

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

(3) Timing of output to SO1n pin (first bit)
When communication is started, the value of transmit buffer register 1n (SOTB1n) is output from the SO1n pin.
The output operation of the first bit at this time is described below.
The first bit is directly latched by the SOTB1n register to the output latch at the falling (or rising) edge of SCK1n,
and output from the SO1n pin via an output selector. Then, the value of the SOTB1n register is transferred to the
SIO1n register at the next rising (or falling) edge of SCK1n, and shifted one bit. At the same time, the first bit of
the receive data is stored in the SIO1n register via the SI1n pin.
The second and subsequent bits are latched by the SIO1n register to the output latch at the next falling (or rising)
edge of SCK1n, and the data is output from the SO1n pin.
The first bit is directly latched by the SOTB1n register at the falling edge of the write signal of the SOTB1n
register or the read signal of the SIO1n register, and output from the SO1n pin via an output selector. Then, the
value of the SOTB1n register is transferred to the SIO1n register at the next falling (or rising) edge of SCK1n, and
shifted one bit. At the same time, the first bit of the receive data is stored in the SIO1n register via the SI1n pin.
The second and subsequent bits are latched by the SIO1n register to the output latch at the next rising (or falling)
edge of SCK1n, and the data is output from the SO1n pin.
Remark n = 0:
n = 0, 1:
Writing to SOTB1n or
Writing to SOTB1n or
reading from SIO1n
reading from SIO1n
Output latch
Output latch
PD78F0132H
PD78F0133H, 78F0134H, 78F0136H, 78F0138H, 78F0138HD
(1) When CKP1n = 0, DAP1n = 0 (or CKP1n = 1, DAP1n = 0)
(2) When CKP1n = 0, DAP1n = 1 (or CKP1n = 1, DAP1n = 1)
SOTB1n
SOTB1n
SCK1n
SCK1n
SIO1n
SIO1n
SO1n
SO1n
CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11
Figure 15-11. Output Operation of First Bit
User’s Manual U16899EJ3V0UD
First bit
First bit
2nd bit
2nd bit
3rd bit
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