UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 545

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

16-bit
timer/
event
counters
00, 01
(TM00,
TM01)
Function
PRM00:
Prescaler mode
register 00
PRM01:
Prescaler mode
register 01
CR01n: 16-bit
timer
capture/compar
e register 01n
CR00n, CR01n:
16-bit timer
capture/compar
e registers 00n,
01n
PPG output
Details of
Function
If the TI000 or TI010 pin is high level immediately after system reset, the rising
edge is immediately detected after the rising edge or both the rising and falling
edges are set as the valid edge(s) of the TI000 pin or TI010 pin to enable the
operation of 16-bit timer counter 00 (TM00). Care is therefore required when
pulling up the TI000 or TI010 pin. However, if the TI000 or TI010 pin is high level
when re-enabling operation after the operation has been stopped, the rising edge
is not detected.
When the valid edge of the TI010 pin is used, P01 cannot be used as the timer
output pin (TO00). When P01 is used as the TO00 pin, the valid edge of the
TI010 pin cannot be used.
When the internal oscillation clock is selected as the clock to be supplied to the
CPU, the clock of the internal oscillator is divided and supplied as the count clock.
If the count clock is the internal oscillation clock, the operation of 16-bit
timer/event counter 00 is not guaranteed. When an external clock is used and
when the internal oscillation clock is selected and supplied to the CPU, the
operation of 16-bit timer/event counter 00 is not guaranteed, either, because the
internal oscillation clock is supplied as the sampling clock to eliminate noise.
Always set data to PRM01 after stopping the timer operation.
If the valid edge of the TI001 pin is to be set for the count clock, do not set the
clear & start mode using the valid edge of the TI001 pin and the capture trigger.
If the TI001 or TI011 pin is high level immediately after system reset, the rising
edge is immediately detected after the rising edge or both the rising and falling
edges are set as the valid edge(s) of the TI001 pin or TI011 pin to enable the
operation of 16-bit timer counter 01 (TM01). Care is therefore required when
pulling up the TI001 or TI011 pin. However, if the TI001 or TI011 pin is high level
when re-enabling operation after the operation has been stopped, the rising edge
is not detected.
When the valid edge of the TI011 pin is used, P06 cannot be used as the timer
output pin (TO01). When P06 is used as the TO01 pin, the valid edge of the
TI011 pin cannot be used.
To change the value of the duty factor (the value of the CR01n register) during
operation, see Caution 2 in Figure 6-20 PPG Output Operation Timing.
Values in the following range should be set in CR00n and CR01n:
0000H
The pulse generated through PPG output has a cycle of [CR00n setting value +
1], and a duty of [(CR01n setting value + 1)/(CR00n setting value + 1)].
In the PPG output operation, change the pulse width (rewrite CR01n) during
TM0n operation using the following procedure.
<1> Disable the timer output inversion operation by match of TM0n and CR01n
<2> Disable the INTTM01n interrupt (TMMK01n = 1)
<3> Rewrite CR01n
<4> Wait for 1 cycle of the TM0n count clock
<5> Enable the timer output inversion operation by match of TM0n and CR01n
<6> Clear the interrupt request flag of INTTM01n (TMIF01n = 0)
<7> Enable the INTTM01n interrupt (TMMK01n = 0)
(TOC0n4 = 0)
(TOC0n4 = 1)
APPENDIX D LIST OF CAUTIONS
CR01n < CR00n
User’s Manual U16899EJ3V0UD
FFFFH
Cautions
p. 151
p. 151
p. 153
p. 153
p. 153
p. 153
p. 153
p. 157
p. 158
p. 158
p. 159
Page
(6/25)
543