UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 126

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

124
High-speed system clock
(f
Internal oscillation
clock (f
Subsystem clock
(f
XP
XT
)
)
Note Check using the oscillation stabilization time counter status register (OSTC).
(a) When the RESET signal is generated, bit 0 of the main clock mode register (MCM) is cleared to 0 and the
(b) After RESET release, the CPU clock can be switched from the internal oscillation clock to the high-speed
(c) Internal oscillator can be set to stopped/oscillating using the internal oscillation mode register (RCM) when
(d) When internal oscillation clock is used as the CPU clock, the high-speed system clock can be set to
(e) Select the high-speed system clock oscillation stabilization time (2
CPU clock
R
)
RESET
internal oscillation clock is set as the CPU clock. However, a clock is supplied to the CPU after 17 clocks of
the internal oscillation clock have elapsed after RESET release (or clock supply to the CPU stops for 17
clocks). During the RESET period, oscillation of the high-speed system clock and internal oscillation clock is
stopped.
system clock using bit 0 (MCM0) of the main clock mode register (MCM) after the high-speed system clock
oscillation stabilization time has elapsed. At this time, check the oscillation stabilization time using the
oscillation stabilization time counter status register (OSTC) before switching the CPU clock. The CPU clock
status can be checked using bit 1 (MCS) of MCM.
“Can be stopped by software” is selected for the internal oscillator by the option byte, if the high-speed
system or subsystem clock is used as the CPU clock. Make sure that MCS is 1 at this time.
stopped/oscillating using the main OSC control register (MOC). Make sure that MCS is 0 at this time.
When the subsystem clock is used as the CPU clock, whether the high-speed system clock stops or
oscillates can be set by the processor clock control register (PCC). In addition, HALT mode can be used
during operation with the subsystem clock, but STOP mode cannot be used (subsystem clock oscillation
cannot be stopped by the STOP instruction).
the oscillation stabilization time select register (OSTS) when releasing STOP mode while high-speed system
clock is being used as the CPU clock. In addition, when releasing STOP mode while RESET is released and
internal oscillation clock is being used as the CPU clock, check the high-speed system clock oscillation
stabilization time using the oscillation stabilization time counter status register (OSTC).
Figure 5-12. Timing Diagram of CPU Default Start Using Internal Oscillator
Operation
stopped: 17/f
High-speed system clock oscillation stabilization time:
R
2
11
CHAPTER 5 CLOCK GENERATOR
/f
XP
Internal oscillation clock
to 2
User’s Manual U16899EJ3V0UD
16
/f
XP
Note
11
/f
XP
, 2
Switched by software
13
High-speed system clock
/f
XP
, 2
14
/f
XP
, 2
15
/f
XP
, 2
16
/f
XP
) using