UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 291

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Therefore, the maximum receivable baud rate at the transmission destination is as follows.
Similarly, the maximum permissible data frame length can be calculated as follows.
Therefore, the minimum receivable baud rate at the transmission destination is as follows.
The permissible baud rate error between UART0 and the transmission destination can be calculated from the
above minimum and maximum baud rate expressions, as follows.
Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock
10
11
8
16
24
31
Minimum permissible data frame length: FLmin = 11
Division Ratio (k)
FLmax = 11
FLmax =
BRmax = (FLmin/11)
BRmin = (FLmax/11)
2. k: Set value of BRGC0
frequency, and division ratio (k). The higher the input clock frequency and the higher the division
ratio (k), the higher the permissible error.
21k – 2
20k
FL
Table 13-5. Maximum/Minimum Permissible Baud Rate Error
FL
k + 2
2
Maximum Permissible Baud Rate Error
k
11
1
1
CHAPTER 13 SERIAL INTERFACE UART0
=
=
FL =
21k + 2
21k
22k
20k
21k
+3.53%
+4.14%
+4.34%
+4.44%
2
User’s Manual U16899EJ3V0UD
2
Brate
k
Brate
2
FL
FL
k
2k
2
Minimum Permissible Baud Rate Error
FL =
21k + 2
2k
3.61%
4.19%
4.38%
4.47%
FL
289