UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 240

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

10.4 Operation of Watchdog Timer
10.4.1 Watchdog timer operation when “internal oscillator cannot be stopped” is selected by option byte
the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped.
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The operation clock of watchdog timer is fixed to the internal oscillation clock.
After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of
The following shows the watchdog timer operation after reset release.
1.
2.
3.
Notes 1.
Caution In this mode, operation of the watchdog timer absolutely cannot be stopped even during STOP
The status after reset release is as follows.
The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
instruction
After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
Operation clock: Internal oscillation clock
Cycle: 2
Counting starts
Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
2.
instruction execution. For 8-bit timer H1 (TMH1), a division of the internal oscillation clock can
be selected as the count source, so clear the watchdog timer using the interrupt request of TMH1
before the watchdog timer overflows after STOP instruction execution. If this processing is not
performed, an internal reset signal is generated when the watchdog timer overflows after STOP
instruction execution.
The operation clock (internal oscillation clock) cannot be changed. If any value is written to bits 3 and
4 (WDCS3, WDCS4) of WDTM, it is ignored.
As soon as WDTM is written, the counter of the watchdog timer is cleared.
Notes 1, 2
18
/f
R
(546.13 ms: At operation with f
.
CHAPTER 10 WATCHDOG TIMER
User’s Manual U16899EJ3V0UD
R
= 480 kHz (MAX.))