UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 144

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

(3) 16-bit timer capture/compare register 01n (CR01n)
Remarks 1. Setting ES0n1, ES0n0 = 1, 0 is prohibited.
142
Falling edge
Rising edge
Both rising and falling edges
CR01n is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is
used as a capture register or a compare register is set by bit 2 (CRC0n2) of capture/compare control register 0n
(CRC0n).
CR01n can be set by a 16-bit memory manipulation instruction.
RESET input clears this register to 0000H.
Cautions 1. If the CR01n register is cleared to 0000H, an interrupt request (INTTM01n) is generated when
When CR01n is used as a compare register
The value set in the CR01n is constantly compared with 16-bit timer counter 0n (TM0n) count value, and an
interrupt request (INTTM01n) is generated if they match. The set value is held until CR01n is rewritten.
When CR01n is used as a capture register
It is possible to select the valid edge of the TI00n pin as the capture trigger. The TI00n pin valid edge is set by
prescaler mode register 0n (PRM0n) (see Table 6-3).
3. n = 0:
CR01n Capture Trigger
2. ES0n1, ES0n0: Bits 5 and 4 of prescaler mode register 0n (PRM0n)
(n = 0, 1)
Address: FF14H, FF15H (CR010), FFB4H, FFB5H (CR011)
Symbol
CR01n
CRC0n2:
n = 0, 1:
2. When CR01n is used as a capture register, read data is undefined if the register read time
3. CR01n can be rewritten during TM0n operation. For details, see Caution 2 in Figure 6-20.
Table 6-3. CR01n Capture Trigger and Valid Edge of TI00n Pin (CRC0n2 = 1)
the value of CR01n changes from 0000H to 0001H following TM0n overflow (FFFFH). In
addition, INTTM01n is generated after a match between TM0n and CR01n, after detecting the
valid edge of the TI00n pin, or the timer is cleared by a one-shot trigger.
and capture trigger input conflict (the capture data itself is the correct value).
If count stop input and capture trigger input conflict, the captured data is undefined.
Figure 6-5. Format of 16-Bit Timer Capture/Compare Register 01n (CR01n)
PD78F0132H
PD78F0133H, 78F0134H, 78F0136H, 78F0138H, 78F0138HD
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Bit 2 of capture/compare control register 0n (CRC0n)
FF15H (CR010)
FFB5H (CR011)
Falling edge
Rising edge
Both rising and falling edges
User’s Manual U16899EJ3V0UD
TI00n Pin Valid Edge
After reset: 0000H
FFB4H (CR011)
FF14H (CR010)
ES0n1
R/W
0
0
1
ES0n0
0
1
1