UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 321

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

R
Remark T
X
(g) Noise filter of receive data
D6/P14
(h) SBF transmission
INTST6
SBTT6
T
The RxD6 signal is sampled with the base clock output by the prescaler block.
If two sampled values are the same, the output of the match detector changes, and the data is sampled as
input data.
Because the circuit is configured as shown in Figure 14-21, the internal processing of the reception operation
is delayed by two clocks from the external signal status.
When the device is incorporated in LIN, the SBF (Synchronous Break Field) transmission control function is
used for transmission.
Operation.
The TxD6 pin outputs a high level when bit 7 (POWER6) of asynchronous serial interface mode register 6
(ASIM6) is set to 1. Transmission is enabled when bit 6 (TXE6) of ASIM6 is set to 1 next time, and SBF
transmission operation is started when bit 5 (SBTT6) of asynchronous serial interface control register 6
(ASICL6) is set to 1.
After transmission has been started, the low levels of bits 13 to 20 (set by bits 4 to 2 (SBL62 to SBL60) of
ASICL6) are output. When SBF transmission is complete, a transmission completion interrupt request
(INTST6) is issued, and SBTT6 is automatically cleared. After SBF transmission is completed, the normal
transmission mode is restored.
SBF transmission is stopped until the data to be transmitted next is written to transmit buffer register 6
(TXB6) or SBTT6 is set to 1.
Base clock
X
D6
INTST6: Transmission completion interrupt request
SBTT6: Bit 5 of asynchronous serial interface control register 6 (ASICL6)
X
D6:
T
X
1
D6 pin (output)
2
In
For the transmission operation of LIN, see Figure 14-1
3
CHAPTER 14 SERIAL INTERFACE UART6
Figure 14-21. Noise Filter Circuit
Figure 14-22. SBF Transmission
4
Q
User’s Manual U16899EJ3V0UD
5
6
Internal signal A
Match detector
7
8
9
10
11
In
LD_EN
12
13
Q
Stop
LIN Transmission
Internal signal B
319