DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 970

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 18 I
18.3.4
ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and
acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits
received.
Rev. 3.00 May 17, 2007 Page 912 of 1582
REJ09B0181-0300
Bit
7
6
5
I
2
Bit Name
TIE
TEIE
RIE
2
C Bus Interrupt Enable Register (ICIER)
C Bus Interface 2 (I
Initial value:
Initial
Value
0
0
0
R/W:
Bit:
2
C2)
R/W
TIE
7
0
R/W
R/W
R/W
R/W
TEIE
R/W
6
0
Description
Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1 or 0, this bit
enables or disables the transmit data empty interrupt
(IITXI).
0: Transmit data empty interrupt request (IITXI) is
1: Transmit data empty interrupt request (IITXI) is
Transmit End Interrupt Enable
This bit enables or disables the transmit end interrupt
(IITEI) at the rising of the ninth clock while the TDRE bit
in ICSR is 1. IITEI can be canceled by clearing the
TEND bit or the TEIE bit to 0.
0: Transmit end interrupt request (IITEI) is disabled.
1: Transmit end interrupt request (IITEI) is enabled.
Receive Interrupt Enable
This bit enables or disables the receive data full
interrupt request (IIRXI) and the overrun error interrupt
request (IIERI) in the clock synchronous format when
receive data is transferred from ICDRS to ICDRR and
the RDRF bit in ICSR is set to 1. IIRXI can be canceled
by clearing the RDRF or RIE bit to 0.
0: Receive data full interrupt request (IIRXI) are
1: Receive data full interrupt request (IIRXI) are
R/W
RIE
5
0
disabled.
enabled.
disabled.
enabled.
NAKIE
R/W
4
0
STIE
R/W
3
0
ACKE ACKBR ACKBT
R/W
2
0
R
1
0
R/W
0
0