DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 737

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

The port output enable (POE) can be used to place the high-current pins (pins multiplexed with
TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D in the MTU2 and TIOC3BS,
TIOC3DS, TIOC4AS, TIOC4BS, TIOC4CS, and TIOC4DS in the MTU2S) and the pins for
channel 0 of the MTU2 (pins multiplexed with TIOC0A, TIOC0B, TIOC0C, and TIOC0D) in
high-impedance state, depending on the change on POE0 to POE8 input pins and the output status
of the high-current pins, or by modifying register settings. It can also simultaneously generate
interrupt requests.
13.1
• Each of the POE0 to POE8 input pins can be set for falling edge, Pφ/8 × 16, Pφ/16 × 16, or
• High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance
• High-current pins can be placed in high-impedance state when the high-current pin output
• High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance
• Interrupts can be generated by input-level sampling or output-level comparison results.
The POE has input level detection circuits, output level comparison circuits, and a high-impedance
request/interrupt request generating circuit as shown in figure 13.1.
In addition to control by the POE, high-current pins can be placed in high-impedance state when
the oscillator stops or in software standby state. For details, refer to section 21.1.11, High-Current
Port Control Register (HCPCR), and appendix A, Pin States.
TIMMTU1A_020020030800
Pφ/128 × 16 low-level sampling.
state by POE0 to POE8 pin falling-edge or low-level sampling.
levels are compared and simultaneous active-level output continues for one cycle or more.
state by modifying the POE register settings.
Features
Section 13 Port Output Enable (POE)
Rev. 3.00 May 17, 2007 Page 679 of 1582
Section 13 Port Output Enable (POE)
REJ09B0181-0300