DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 378

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
Single Read: A read access ends in one cycle when the data bus width is larger than or equal to
access size. This is called single read. As the burst length is set to 1 in SDRAM burst read/single
write mode, only the required data is output. Consequently, no unnecessary bus cycles are
generated.
Figure 9.19 shows the single read basic timing.
Rev. 3.00 May 17, 2007 Page 320 of 1582
REJ09B0181-0300
Figure 9.19 Single Read Basic Timing (Auto-Precharge)
RASL, RASU
CASL, CASU
A12/A11*
Notes: 1.
D31 to D0
A25 to A0
DACKn*
DQMxx
RDWR
CSn
CK
BS
2.
1
2
Address pin to be connected to pin A10 of SDRAM.
The waveform for DACKn is when active low is specified.
Tr
Tc1
Td1
Tde
Tap