DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 12

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 7 User Break Controller (UBC)............................................................ 135
7.1
7.2
7.3
7.4
7.5
Section 8 Data Transfer Controller (DTC)........................................................ 171
8.1
8.2
Rev. 3.00 May 17, 2007 Page xii of lviii
Features.............................................................................................................................. 135
Input/Output Pins............................................................................................................... 137
Register Descriptions......................................................................................................... 138
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10 Break Bus Cycle Register B (BBRB) ................................................................... 148
7.3.11 Break Control Register (BRCR) ........................................................................... 150
7.3.12 Execution Times Break Register (BETR) (Only in F-ZTAT Version)................. 155
7.3.13 Branch Source Register (BRSR) (Only in F-ZTAT Version)............................... 156
7.3.14 Branch Destination Register (BRDR) (Only in F-ZTAT Version)....................... 157
Operation ........................................................................................................................... 158
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
Usage Notes ....................................................................................................................... 168
Features.............................................................................................................................. 171
Register Descriptions......................................................................................................... 173
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
Break Address Register A (BARA)...................................................................... 139
Break Address Mask Register A (BAMRA)......................................................... 139
Break Bus Cycle Register A (BBRA)................................................................... 140
Break Data Register A (BDRA) (Only in F-ZTAT Version)................................ 142
Break Data Mask Register A (BDMRA) (Only in F-ZTAT Version) .................. 143
Break Address Register B (BARB) ...................................................................... 144
Break Address Mask Register B (BAMRB) ......................................................... 145
Break Data Register B (BDRB) (Only in F-ZTAT Version) ................................ 146
Break Data Mask Register B (BDMRB) (Only in F-ZTAT Version)................... 147
Flow of the User Break Operation ........................................................................ 158
User Break on Instruction Fetch Cycle ................................................................. 159
User Break on Data Access Cycle ........................................................................ 160
Sequential Break................................................................................................... 161
Value of Saved Program Counter ......................................................................... 161
PC Trace ............................................................................................................... 162
Usage Examples.................................................................................................... 163
DTC Mode Register A (MRA) ............................................................................. 174
DTC Mode Register B (MRB).............................................................................. 175
DTC Source Address Register (SAR)................................................................... 177
DTC Destination Address Register (DAR)........................................................... 177
DTC Transfer Count Register A (CRA) ............................................................... 178
DTC Transfer Count Register B (CRB)................................................................ 179
DTC Enable Registers A to E (DTCERA to DTCERE) ....................................... 180
DTC Control Register (DTCCR) .......................................................................... 181
DTC Vector Base Register (DTCVBR)................................................................ 183