DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 542

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.11 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and
TADCORA_4 and TADCORB_4 are 16-bit readable/writable registers. When the TCNT_4 count
reaches the value in TADCORA_4 or TADCORB_4, a corresponding A/D converter start request
will be issued.
TADCORA_4 and TADCORB_4 are initialized to H'FFFF.
Initial value:
11.3.12 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4
TADCOBRA_4 and TADCOBRB_4 are 16-bit readable/writable registers. When the crest or
trough of the TCNT_4 count is reached, these register values are transferred to TADCORA_4 and
TADCORB_4, respectively.
TADCOBRA_4 and TADCOBRB_4 are initialized to H'FFFF.
Initial value:
Rev. 3.00 May 17, 2007 Page 484 of 1582
REJ09B0181-0300
Note:
Note:
R/W:
R/W:
Bit:
Bit:
TADCORA_4 and TADCORB_4 must not be accessed in eight bits; they should always be accessed in 16 bits.
TADCOBRA_4 and TADCOBRB_4 must not be accessed in eight bits; they should always be accessed in 16 bits.
R/W
R/W
TADCORB_4)
and TADCOBRB_4)
15
15
1
1
R/W
R/W
14
14
1
1
R/W
R/W
13
13
1
1
R/W
R/W
12
12
1
1
R/W
R/W
11
11
1
1
R/W
R/W
10
10
1
1
R/W
R/W
9
1
9
1
R/W
R/W
8
1
8
1
R/W
R/W
7
1
7
1
R/W
R/W
6
1
6
1
R/W
R/W
5
1
5
1
R/W
R/W
4
1
4
1
R/W
R/W
3
1
3
1
R/W
R/W
2
1
2
1
R/W
R/W
1
1
1
1
R/W
R/W
0
1
0
1