DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 34

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Figure 11.60 Example of Synchronous Clearing in Dead Time during Down-Counting
Figure 11.61 Example of Synchronous Clearing in Interval Tb at Trough
Figure 11.62 MTU2–MTU2S Synchronous Clearing-Suppressed Interval Specified
Figure 11.63 Example of Procedure for Suppressing MTU2–MTU2S Synchronous
Figure 11.64 Example of Synchronous Clearing in Dead Time during Up-Counting
Figure 11.65 Example of Synchronous Clearing in Interval Tb at Crest
Figure 11.66 Example of Synchronous Clearing in Dead Time during Down-Counting
Figure 11.67 Example of Synchronous Clearing in Interval Tb at Trough
Figure 11.68 Example of Counter Clearing Operation by TGRA_3 Compare Match................ 581
Figure 11.69 Example of Output Phase Switching by External Input (1)................................... 582
Figure 11.70 Example of Output Phase Switching by External Input (2)................................... 583
Figure 11.71 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1).. 583
Figure 11.72 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2).. 584
Figure 11.73 Example of Interrupt Skipping Operation Setting Procedure................................ 585
Figure 11.74 Periods during which Interrupt Skipping Count can be Changed ......................... 586
Figure 11.75 Example of Interrupt Skipping Operation ............................................................. 586
Figure 11.76 Example of Operation when Buffer Transfer is Suppressed
Figure 11.77 Example of Operation when Buffer Transfer is Linked with Interrupt Skipping
Figure 11.78 Relationship between Bits T3AEN and T4VEN in TITCR and Buffer Transfer-
Figure 11.79 Example of Procedure for Specifying A/D Converter Start Request Delaying
Figure 11.80 Basic Example of A/D Converter Start Request Signal (TRG4AN) Operation .... 592
Figure 11.81 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked
Rev. 3.00 May 17, 2007 Page xxxiv of Iviii
(Timing (8) in Figure 11.56; Bit WRE of TWCR is 1) ......................................... 573
(Timing (11) in Figure 11.56; Bit WRE of TWCR is 1) ....................................... 574
by SCC Bit in TWCR ............................................................................................ 575
Counter Clearing ................................................................................................... 576
(Timing (3) in Figure 11.56; Bit WRE is 1 and Bit SCC is 1 in TWCR of
MTU2S)................................................................................................................. 577
(Timing (6) in Figure 11.56; Bit WRE is 1 and Bit SCC is 1 in TWCR
of MTU2S) ............................................................................................................ 578
(Timing (8) in Figure 11.56; Bit WRE is 1 and Bit SCC is 1 in TWCR
of MTU2S) ............................................................................................................ 579
(Timing (11) in Figure 11.56; Bit WRE is 1 and Bit SCC is 1 in TWCR of
MTU2S)................................................................................................................. 580
(BTE1 = 0 and BTE0 = 1) ..................................................................................... 588
(BTE1 = 1 and BTE0 = 0) ..................................................................................... 589
Enabled Period....................................................................................................... 589
Function................................................................................................................. 591
with Interrupt Skipping.......................................................................................... 593