DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 520

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.4
TCNTCMPCLR is an 8-bit readable/writable register that specifies requests to clear TCNTU_5,
TCNTV_5, and TCNTW_5. The MTU2 has one TCNTCMPCLR in channel 5.
Rev. 3.00 May 17, 2007 Page 462 of 1582
REJ09B0181-0300
Bit
7 to 3
2
1
Bit Name
—
CMPCLR5U 0
CMPCLR5V 0
Timer Compare Match Clear Register (TCNTCMPCLR)
Initial value:
Initial
Value
All 0
R/W:
Bit:
R
7
0
-
R/W
R
R/W
R/W
R
6
0
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
TCNT Compare Clear 5U
Enables or disables requests to clear TCNTU_5 at
TGRU_5 compare match or input capture.
0: Disables TCNTU_5 to be cleared to H'0000 at
1: Enables TCNTU_5 to be cleared to H'0000 at
TCNT Compare Clear 5V
Enables or disables requests to clear TCNTV_5 at
TGRV_5 compare match or input capture.
0: Disables TCNTV_5 to be cleared to H'0000 at
1: Enables TCNTV_5 to be cleared to H'0000 at
R
5
0
-
TCNTU_5 and TGRU_5 compare match or input
capture
TCNTU_5 and TGRU_5 compare match or input
capture
TCNTV_5 and TGRV_5 compare match or input
capture
TCNTV_5 and TGRV_5 compare match or input
capture
R
4
0
-
R
3
0
-
CLR5U
CMP
R/W
2
0
CLR5V
R/W
CMP
1
0
CLR5W
R/W
CMP
0
0