DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 317

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

(4)
When SDRAM is selected in areas 2 and 3, the WTRP1/0, WTRCD0/1, TRWL1/0, and WTRC1/0
bit settings are effective in both areas in common. When SDRAM should be connected to only one
area, select area 3 for SDRAM connection. In this case, the normal space or SRAM with byte
selection must be selected for area 2.
• CS2WCR
Initial value:
Initial value:
Bit
1, 0
Bit
31 to 11 
10
R/W:
R/W:
SDRAM
Bit:
Bit:
Bit Name

31
15
R
R
Bit Name
HW[1:0]
0
0
-
-
30
14
R
R
0
0
-
-
Initial
Value
All 0
1
29
13
R
R
0
0
-
-
Initial
Value
00
28
12
R
R
0
0
-
-
R/W
R
R
27
11
R
R
0
0
-
-
R/W
R/W
26
10
R
R
0
1
-
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Reserved
This bit is always read as 1. The write value should
always be 1.
Description
Delay Cycles from RD and WRxx Negation to Address
and CSn Negation
Specify the number of delay cycles from RD and WRxx
negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
25
R
R
0
9
0
-
-
R/W
24
R
0
8
1
-
A2CL[1:0]
R/W
23
R
0
7
0
-
Rev. 3.00 May 17, 2007 Page 259 of 1582
22
R
R
0
6
0
-
-
Section 9 Bus State Controller (BSC)
21
R
R
0
5
0
-
-
20
R
R
0
4
0
-
-
19
R
R
0
3
0
-
-
REJ09B0181-0300
18
R
R
0
2
0
-
-
17
R
R
0
1
0
-
-
16
R
R
0
0
0
-
-