DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 461

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

(1) When channel 0 transfers
(2) When channel 1 transfers
(3) When channel 2 transfers
(4) When channel 3 transfers
Initial priority order
Priority order
after transfer
Initial priority order
Priority order
after transfer
Initial priority order
Priority order
after transfer
Post-transfer priority order
when there is an
immediate transfer
request to channel 1 only
Initial priority order
Priority order
after transfer
Figure 10.3 Round-Robin Mode
CH0 > CH1 > CH2 > CH3
CH0 > CH1 > CH2 > CH3
CH0 > CH1 > CH2 > CH3
CH0 > CH1 > CH2 > CH3
CH0 > CH1 > CH2 > CH3
CH3 > CH0 > CH1 > CH2
CH2 > CH3 > CH0 > CH1
CH1 > CH2 > CH3 > CH0
CH2 > CH3 > CH0 > CH1
Section 10 Direct Memory Access Controller (DMAC)
Channel 0 becomes bottom
priority
Channel 1 becomes bottom
priority.
The priority of channel 0, which
was higher than channel 1, is also
shifted.
Channel 2 becomes bottom
priority.
The priority of channels 0 and 1,
which were higher than channel 2,
are also shifted. If immediately
after there is a request to transfer
channel 1 only, channel 1 becomes
bottom priority and the priority of
channels 3 and 0, which were
higher than channel 1, are also
shifted.
Priority order does not change.
Rev. 3.00 May 17, 2007 Page 403 of 1582
REJ09B0181-0300