DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 778

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 14 Watchdog Timer (WDT)
14.4
14.4.1
The WDT can be used to revoke software standby mode with an NMI interrupt or external
interrupt (IRQ). The procedure is described below. (The WDT does not run when resets are used
for revoking, so keep the RES pin low until the clock stabilizes.)
1. Before transition to software standby mode, always clear the TME bit in WTCSR to 0. When
2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for
3. Transition to software standby mode by executing a SLEEP instruction to stop the clock.
4. The WDT starts counting by detecting a change in the level input to the NMI or IRQ pin.
5. When the WDT count overflows, the CPG starts supplying the clock and the LSI resumes
14.4.2
While operating in watchdog timer mode, the WDT generates an internal reset of the type
specified by the RSTS bit in WTCSR and asserts a signal through the WDTOVF pin every time
the counter overflows.
1. Set the WT/IT bit in WTCSR to 1, set the reset type in the RSTS bit, set the type of count
2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode.
3. While operating in watchdog timer mode, rewrite the counter periodically to prevent the
4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1, asserts a signal
Rev. 3.00 May 17, 2007 Page 720 of 1582
REJ09B0181-0300
the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the
count overflows.
the counter in the WTCNT counter. These values should ensure that the time till count
overflow is longer than the clock oscillation settling time.
operation. The WOVF flag in WTCSR is not set when this happens.
clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT
counter.
counter from overflowing.
through the WDTOVF pin for one cycle of the count clock specified by the CKS2 to CKS0
bits, and generates a reset of the type specified by the RSTS bit. The counter then resumes
counting.
Operation
Revoking Software Standbys
Using Watchdog Timer Mode