DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 845

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

15.7.6
When the external clock source is used for the clock for synchronization, input the external clock
after waiting for five or more cycles of the peripheral operating clock after SCTDR is modified
through the DMAC or DTC. If a transmit clock is input within four cycles after SCTDR is
modified, a malfunction may occur (figure 15.22).
When data is written to SCTDR by activating the DMAC or DTC by a TXI interrupt, the TEND
flag value becomes undefined. In this case, do not use the TEND flag as the transmit end flag.
15.7.7
TE and RE must be set to 1 after waiting for four or more cycles of the peripheral operating clock
after the SCK external clock is changed from 0 to 1.
TE and RE must be set to 1 only while the SCK external clock is 1.
15.7.8
SCI operation can be disabled or enabled using the standby control register. The initial setting is
for SCI operation to be halted. Register access is enabled by clearing module standby mode. For
details, refer to section 26, Power-Down Modes.
TDRE
SCK
Figure 15.22 Example of Clock Synchronous Transfer Using DMAC or DTC
TXD
Note: When using the external clock, t must be set to larger than 4 cycles.
Note on Using DMAC or DTC
Note on Using External Clock in Clock Synchronous Mode
Module Standby Mode Setting
t
D0
D1
D2
D3
Section 15 Serial Communication Interface (SCI)
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Rev. 3.00 May 17, 2007 Page 787 of 1582
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