DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 337

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

9.4.8
BSCEHR is a 16-bit register that specifies the timing of bus release by the DTC and DMAC. It
also specifies the application of priority in transfer operations and enables or disables the functions
that have the effect of decreasing numbers of cycles over which the DTC is active. The differences
in DTC operation made by the combinations of the DTLOCK, CSSTP1, and DTBST bits settings
are described in 8.5.9, DTC Bus Releasing Timing.
Setting the CSSTP2 bit can improve the transfer performance of the DMAC in burst-mode transfer
and of the DTC when the DTLOCK bit is 0.
Furthermore, setting the CSSTP3 bit selects whether or not access to the external space by the
CPU takes priority over DTC or DMAC transfer in cycle-steal mode. The DTC short address
mode is implemented by setting the DTSA bit. For details of the short address mode, see section
8.4, Location of Transfer Information and DTC Vector Table.
A DTC activation priority order can be set up for the DTC activation sources. The DTPR bit
selects whether or not this priority order is valid or invalid when multiple sources issue activation
requests before DTC activation. The corresponding bit from among DMMTU4 to DMMTU0 must
be set for MTU2-triggered transfer by the DMAC in the burst mode. Do not modify this register
while the DMAC or DTC is active.
Initial value:
Bit
15
R/W:
Bit:
DTLOCK CSSTP1
Bit Name
DTLOCK
R/W
Bus Function Extending Register (BSCEHR)
15
0
R/W
14
0
13
Initial
Value
0
R
0
-
CSSTP2
R/W
12
0
DTBST DTSA
R/W
R/W
R/W
11
0
R/W
10
0
Description
DTC Lock Enable
Specifies the timing of bus release by the DTC.
0: The DTC releases the bus on generation of the NOP
1: The DTC releases the bus after vector read, on
CSSTP3
R/W
cycle that follows vector read or write-back of transfer
information.
generation of the NOP cycle that follows vector read,
after transfer information read, after a round of data
transfer, or after write-back of transfer information.
9
0
DTPR
R/W
8
0
R
7
0
-
Rev. 3.00 May 17, 2007 Page 279 of 1582
R
6
0
-
Section 9 Bus State Controller (BSC)
R
5
0
-
DMMTU4 DMMTU3 DMMTU2 DMMTU1 DMMTU0
R/W
4
0
R/W
3
0
REJ09B0181-0300
R/W
2
0
R/W
1
0
R/W
0
0