DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 584

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Selecting Timing for Transfer from Buffer Registers to Timer General Registers in Buffer
Operation: The timing for transfer from buffer registers to timer general registers can be selected
in PWM mode 1 or 2 for channel 0 or in PWM mode 1 for channels 3 and 4 by setting the buffer
operation transfer mode registers (TBTM_0, TBTM_3, and TBTM_4). Either compare match
(initial setting) or TCNT clearing can be selected for the transfer timing. TCNT clearing as
transfer timing is one of the following cases.
• When TCNT overflows (H'FFFF to H'0000)
• When H'0000 is written to TCNT during counting
• When TCNT is cleared to H'0000 under the condition specified in the CCLR2 to CCLR0 bits
Note: TBTM must be modified only while TCNT stops.
Figure 11.19 shows an operation example in which PWM mode 1 is designated for channel 0 and
buffer operation is designated for TGRA_0 and TGRC_0. The settings used in this example are
TCNT_0 clearing by compare match B, 1 output at compare match A, and 0 output at compare
match B. The TTSA bit in TBTM_0 is set to 1.
Rev. 3.00 May 17, 2007 Page 526 of 1582
REJ09B0181-0300
in TCR
H'0F07
H'09FB
H'0532
H'0000
TIOCA
TGRA
TGRC
TCNT value
Figure 11.18 Example of Buffer Operation (2)
H'0532
H'0F07
H'0532
H'09FB
H'0F07
Time