DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 825

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

In clock synchronous serial communication, each data bit is output on the communication line
from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of
the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first)
to the MSB (last). After output of the MSB, the communication line remains in the state of the
MSB. In clock synchronous mode, the SCI transmits or receives data by synchronizing with the
rising edge of the serial clock.
(1)
The data length is fixed at eight bits. No parity bit can be added.
(2)
An internal clock generated by the on-chip baud rate generator or an external clock input from the
SCK pin can be selected as the SCI transmit/receive clock. For selection of the SCI clock source,
see table 15.14.
When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock
pulses are output per transmitted or received character. When the SCI does not perform
transmission or reception, the clock signal remains in the high state. When only reception is
performed, output of the synchronous clock continues until an overrun error occurs or the RE bit is
cleared to 0. For the reception of n characters, select the external clock as the clock source. If the
internal clock has to be used, set RE and TE to 1, then transmit n characters of dummy data at the
same time as receiving the n characters of data.
(3)
SCI Initialization (Clock Synchronous Mode): Before transmitting, receiving, or changing the
mode or communication format, the software must clear the TE and RE bits to 0 in the serial
control register (SCSCR), then initialize the SCI. Clearing TE to 0 sets the TDRE flag to 1 and
initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does not initialize the
RDRF, PER, FER, and ORER flags and receive data register (SCRDR), which retain their
previous contents.
Communication Format
Clock
Transmitting and Receiving Data
Section 15 Serial Communication Interface (SCI)
Rev. 3.00 May 17, 2007 Page 767 of 1582
REJ09B0181-0300