DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 232

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 8 Data Transfer Controller (DTC)
8.2.1
MRA selects DTC operating mode. MRA cannot be accessed directly by the CPU.
Rev. 3.00 May 17, 2007 Page 174 of 1582
REJ09B0181-0300
Bit
7, 6
5, 4
3, 2
Bit Name
MD[1:0]
Sz[1:0]
SM[1:0]
DTC Mode Register A (MRA)
Initial
Value
Undefined 
Undefined 
Undefined 
Initial value:
R/W:
Bit:
R/W
7
-
-
MD[1:0]
6
-
-
Description
DTC Mode 1 and 0
Specify DTC transfer mode.
00: Normal mode
01: Repeat mode
10: Block transfer mode
11: Setting prohibited
DTC Data Transfer Size 1 and 0
Specify the size of data to be transferred.
00: Byte-size transfer
01: Word-size transfer
10: Longword-size transfer
11: Setting prohibited
Source Address Mode 1 and 0
Specify an SAR operation after a data transfer.
0x: SAR is fixed
10: SAR is incremented after a transfer
11: SAR is decremented after a transfer
(SAR writeback is skipped)
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
5
-
-
Sz[1:0]
4
-
-
3
-
-
SM[1:0]
2
-
-
1
-
-
-
0
-
-
-