DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 418

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
Table 9.30 Minimum Number of Idle Cycles between Access Cycles during DMAC Dual
Notes: DMAC and DTC are driven by Bφ. The minimum number of idle cycles is not affected by
Rev. 3.00 May 17, 2007 Page 360 of 1582
REJ09B0181-0300
CSnWCR.
WM Setting
1
0
1
0
1
0
1
0
BSC Register Setting
changing a clock ratio.
1. Minimum number of idle cycles between the word access to address 0 and the word
2. Other than the above cases.
access to address 2 in the 32-bit access with a 16-bit bus width,
minimum number of idle cycles between the byte access to address 0 and the byte
access to address 1 in the 16-bit access with an 8-bit bus width,
minimum number of idle cycles between the byte accesses to address 0, to address 1,
to address 2, and to address 3 in the 32-bit access with an 8-bit bus width, and
minimum number of idle cycles between consecutive accesses in 16-byte transfer.
CSnBCR
Idle Setting
0
0
1
1
2
2
4
4
Address Mode and DTC Transfer for the Normal Space Interface
Read to
Write
2
2
2
2
2
2
4
4
When Access Size is
Less than Bus Width
Write to
Read
0
1
1
1
2
2
4
4
Continuous
Read*
0
1
1
1
2
2
4
4
When Access Size Exceeds Bus Width
1
Read to
Write*
2
2
2
2
2
2
4
4
2
Continuous
Write*
0
1
1
1
2
2
4
4
1
Write to
Read*
0
1
1
1
2
2
4
4
2