DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 372

IC SUPERH MCU FLASH 112LQFP

DF70844AD80FPV

Manufacturer Part Number
DF70844AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet

Specifications of DF70844AD80FPV

Core Size
32-Bit
Program Memory Size
256KB (256K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
16KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF70844AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
DF70844AD80FPV
Quantity:
5 000
Section 9 Bus State Controller (BSC)
Table 9.24 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0],
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
Rev. 3.00 May 17, 2007 Page 314 of 1582
REJ09B0181-0300
BSZ[1:0]
10 (16 bits)
Output Pin of
This LSI
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Example of connected memory
256-Mbit product (4 Mwords × 16 bits × 4 banks, column 10 bits product): 1
2. Bank address specification
access mode.
A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (5)-2
A2ROW[1:0]/
A3ROW[1:0]
01 (12 bits)
Row Address
Output Cycle
A27
A26
A25
A24*
A23*
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
2
2
Setting
A2COL[1:0]/
A3COL[1:0]
10 (10 bits)
Column Address
Output Cycle
A17
A16
A15
A24*
A23*
A12
L/H*
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
2
2
SDRAM Pin
A13 (BA1)
A12 (BA0)
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Function
Unused
Specifies bank
Address
Specifies
address/precharge
Address
Unused

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