DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 847

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

This LSI has a channel serial communication interface with FIFO (SCIF) that supports both
asynchronous and clock synchronous serial communication. It also has 16-stage FIFO registers for
both transmission and reception independently that enable this LSI to perform efficient high-speed
continuous communication.
16.1
• Asynchronous serial communication:
• Clock Synchronous mode:
• Full duplex communication: The transmitting and receiving sections are independent, so the
• On-chip baud rate generator with selectable bit rates
• Internal or external transmit/receive clock source: From either baud rate generator (internal) or
SCIS3C4A_000020030900
 Serial data communication is performed by start-stop in character units. The SCIF can
 Data length: 7 or 8 bits
 Stop bit length: 1 or 2 bits
 Parity: Even, odd, or none
 Receive error detection: Parity, framing, and overrun errors
 Break detection: Break is detected when a framing error is followed by at least one frame at
 Serial data communication is synchronized with a clock signal. The SCIF can communicate
 Data length: 8 bits
 Receive error detection: Overrun errors
SCIF can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so
high-speed continuous data transfer is possible in both the transmit and receive directions.
SCK pin (external)
Section 16 Serial Communication Interface with FIFO
communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous
communication interface adapter (ACIA), or any other communications chip that employs
a standard asynchronous serial system. There are eight selectable serial data
communication formats.
the space 0 level (low level). It is also detected by reading the RXD level directly from the
serial port data register when a framing error occurs.
with other chips having a clock synchronous communication function. There is one serial
data communication format.
Features
(SCIF)
Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 May 17, 2007 Page 789 of 1582
REJ09B0181-0300