DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 453

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Bit
9, 8
7 to 3
2
1
Bit Name
PR[1:0]
—
AE
NMIF
Initial
Value
00
All 0
0
0
R/W
R/W
R
R/(W)* Address Error Flag
R/(W)* NMI Flag
Description
Priority Mode 1, 0
Select the priority level between channels when there are
transfer requests for multiple channels simultaneously.
00: CH0 > CH1 > CH2 > CH3
01: CH0 > CH2 > CH3 > CH1
10: Setting prohibited
11: Round-robin mode
Reserved
These bits are always read as 0. The write value should
always be 0.
Indicates that an address error occurred during DMA
transfer. If this bit is set, DMA transfer is disabled even if
the DE bit in CHCR and the DME bit in DMAOR are set to
1. This bit can only be cleared by writing 0 after reading
1.
0: No DMAC address error
[Clearing condition]
•
1: DMAC address error occurs
Indicates that an NMI interrupt occurred. If this bit is set,
DMA transfer is disabled even if the DE bit in CHCR and
the DME bit in DMAOR are set to 1. This bit can only be
cleared by writing 0 after reading 1.
When the NMI is input, the DMA transfer in progress can
be done in one transfer unit. When the DMAC is not in
operational, the NMIF bit is set to 1 even if the NMI
interrupt was input.
0: No NMI interrupt
[Clearing condition]
•
1: NMI interrupt occurs
Writing AE = 0 after AE = 1 read
Writing NMIF = 0 after NMIF = 1 read
Section 10 Direct Memory Access Controller (DMAC)
Rev. 3.00 May 17, 2007 Page 395 of 1582
REJ09B0181-0300