DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 943

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

[1]
[2]
[3]
[4]
Data transferred from SSTDR to SSTRSR
Set TDRE to 1 to start transmission
Confirm that TEND is cleared to 0
Write transmit data to SSTDR
TDRE automatically cleared
Consecutive data transmission?
Clear TE in SSER to 0
Read TDRE in SSSR
Read TEND in SSSR
quantum elapsed?
End transmission
Figure 17.6 Flowchart Example of Data Transmission (SSU Mode)
Clear TEND to 0
Initial setting
One bit time
TDRE = 1?
TEND = 1?
Yes
Yes
Yes
No
Start
Yes
No
No
No
Section 17 Synchronous Serial Communication Unit (SSU)
[1] Initial setting:
[2] Check that the SSU state and write transmit data:
[3] Procedure for consecutive data transmission:
[4] Procedure for data transmission end:
Specify the transmit data format.
Write transmit data to SSTDR after reading and confirming
that the TDRE bit is 1. The TDRE bit is automatically cleared
to 0 and transmission is started by writing data to SSTDR.
To continue data transmission, confirm that the TDRE bit is 1
meaning that SSTDR is ready to be written to. After that, data
can be written to SSTDR. The TDRE bit is automatically
cleared to 0 by writing data to SSTDR.
To end data transmission, confirm that the TEND bit is cleared
to 0. After completion of transmitting the last bit, clear the TE
bit to 0.
Note: Hatching boxes represent SSU internal operations.
Rev. 3.00 May 17, 2007 Page 885 of 1582
REJ09B0181-0300