C8051F902-GM Silicon Laboratories Inc, C8051F902-GM Datasheet - Page 27

• Manufacturer Part Number: C8051F902-GM
• Description: IC MCU 8BIT 8KB FLASH 24QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F9xxr

Specifications of C8051F902-GM

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 24-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 15x10/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F9x
• Core: 8051
• Data Ram Size: 768 B
• Interface Type: UART
• Maximum Clock Frequency: 25 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F912DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Package: 24QFN EP
• Device Core: 8051
• Family Name: C8051F90x
• Maximum Speed: 25 MHz
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1848-5

3.
*Note: Available only on the C8051F912/02.
DCEN
Name
C2CK
VBAT
DC– /
V
GND
GND
RST/
P2.7/
DC+
C2D
DD
Pinout and Package Definitions
/
‘F912-GM
‘F902-GM
‘F911-GM
‘F901-GM
Pin Numbers
5
3
1
2
4
6
7
Table 3.1. Pin Definitions for the C8051F91x-C8051F90x
‘F912-GU
‘F902-GU
‘F911-GU
‘F901-GU
10
8
6
4
5
7
9
P Out
Type
D I/O
D I/O
D I/O
D I/O
P In
P In
P In
P In
G
G
G
Description
Battery Supply Voltage.
C8051F911/01 devices:
Must be 0.9 to 1.8 V in single-cell battery mode and 1.8 to 3.6 V in
dual-cell battery mode.
C8051F912/02 devices:
Must be 0.9 to 3.6 V in single-cell battery mode and 1.8 to 3.6 V in
dual-cell battery mode.
Power Supply Voltage. Must be 1.8 to 3.6 V. This supply voltage is
not required in low power sleep mode. This voltage must always
be > VBAT.
Positive output of the dc-dc converter. In single-cell battery mode,
a 1uF ceramic capacitor is required between DC+ and DC–. This
pin can supply power to external devices when operating in single-
cell battery mode.
DC-DC converter return current path. In single-cell battery mode,
this pin is typically not connected to ground.
In dual-cell battery mode, this pin must be connected directly to
ground.
Required Ground.
DC-DC Enable Pin. In single-cell battery mode, this pin must be
connected to VBAT through a 0.68 µH inductor.
In dual-cell battery mode, this pin must be connected directly to
ground.
Device Reset. Open-drain output of internal POR or V
An external source can initiate a system reset by driving this pin
low for at least 15 µs. A 1 k to 5 k pullup to V
mended. See Section “18. Reset Sources” on page 171 Section
for a complete description.
Clock signal for the C2 Debug Interface.
Port 2.7. This pin can only be used as GPIO. The Crossbar cannot
route signals to this pin and it cannot be configured as an analog
input. See Port I/O Section for a complete description.
Bi-directional data signal for the C2 Debug Interface.
Rev. 1.0
C8051F91x-C8051F90x
DD
is recom-
DD
monitor.
27