C8051F902-GM Silicon Laboratories Inc, C8051F902-GM Datasheet - Page 10

• Manufacturer Part Number: C8051F902-GM
• Description: IC MCU 8BIT 8KB FLASH 24QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F9xxr

Specifications of C8051F902-GM

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 24-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 15x10/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F9x
• Core: 8051
• Data Ram Size: 768 B
• Interface Type: UART
• Maximum Clock Frequency: 25 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F912DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Package: 24QFN EP
• Device Core: 8051
• Family Name: C8051F90x
• Maximum Speed: 25 MHz
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1848-5

C8051F91x-C8051F90x
10
Figure 13.1. Flash Program Memory Map (16 kB and 8 kB devices)..................... 134
Figure 14.1. C8051F91x-C8051F90x Power Distribution....................................... 144
Figure 15.1. CRC0 Block Diagram ......................................................................... 152
Figure 15.2. Bit Reverse Register .......................................................................... 159
Figure 16.1. DC-DC Converter Block Diagram....................................................... 160
Figure 16.2. DC-DC Converter Configuration Options ........................................... 163
Figure 18.1. Reset Sources.................................................................................... 171
Figure 18.2. Power-Fail Reset Timing Diagram ..................................................... 172
Figure 18.3. Power-Fail Reset Timing Diagram ..................................................... 173
Figure 19.1. Clocking Sources Block Diagram ....................................................... 179
Figure 19.2. 25 MHz External Crystal Example...................................................... 181
Figure 20.1. SmaRTClock Block Diagram.............................................................. 188
Figure 20.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results.......... 197
Figure 21.1. Port I/O Functional Block Diagram ..................................................... 205
Figure 21.2. Port I/O Cell Block Diagram ............................................................... 206
Figure 21.3. Crossbar Priority Decoder with No Pins Skipped ............................... 210
Figure 21.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 211
Figure 22.1. SMBus Block Diagram ....................................................................... 225
Figure 22.2. Typical SMBus Configuration ............................................................. 226
Figure 22.3. SMBus Transaction ............................................................................ 227
Figure 22.4. Typical SMBus SCL Generation......................................................... 230
Figure 22.5. Typical Master Write Sequence ......................................................... 239
Figure 22.6. Typical Master Read Sequence ......................................................... 240
Figure 22.7. Typical Slave Write Sequence ........................................................... 241
Figure 22.8. Typical Slave Read Sequence ........................................................... 242
Figure 23.1. UART0 Block Diagram ....................................................................... 247
Figure 23.2. UART0 Baud Rate Logic .................................................................... 248
Figure 23.3. UART Interconnect Diagram .............................................................. 249
Figure 23.4. 8-Bit UART Timing Diagram............................................................... 249
Figure 23.5. 9-Bit UART Timing Diagram............................................................... 250
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram .......................... 251
Figure 24.1. SPI Block Diagram ............................................................................. 255
Figure 24.2. Multiple-Master Mode Connection Diagram ....................................... 258
Figure 24.3. 3-Wire Single Master and 3-Wire Single Slave Mode 
Figure 24.4. 4-Wire Single Master Mode and 4-Wire Slave Mode 
Figure 24.5. Master Mode Data/Clock Timing ........................................................ 260
Figure 24.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 261
Figure 24.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 261
Figure 24.8. SPI Master Timing (CKPHA = 0)........................................................ 267
Figure 24.9. SPI Master Timing (CKPHA = 1)........................................................ 267
Figure 24.10. SPI Slave Timing (CKPHA = 0)........................................................ 268
Figure 24.11. SPI Slave Timing (CKPHA = 1)........................................................ 268
Figure 25.1. T0 Mode 0 Block Diagram.................................................................. 273
Connection Diagram ........................................................................... 258
Connection Diagram........................................................................... 258
Rev. 1.0