C8051F902-GM Silicon Laboratories Inc, C8051F902-GM Datasheet - Page 221

• Manufacturer Part Number: C8051F902-GM
• Description: IC MCU 8BIT 8KB FLASH 24QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F9xxr

Specifications of C8051F902-GM

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 24-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 15x10/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F9x
• Core: 8051
• Data Ram Size: 768 B
• Interface Type: UART
• Maximum Clock Frequency: 25 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F912DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Package: 24QFN EP
• Device Core: 8051
• Family Name: C8051F90x
• Maximum Speed: 25 MHz
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1848-5

SFR Definition 21.13. P1: Port1
SFR Page = All Pages; SFR Address = 0x90; Bit-Addressable
SFR Definition 21.14. P1SKIP: Port1 Skip
SFR Page = 0x0; SFR Address = 0xD5
Name
Reset
Name
Reset
Type
Type
Bit
6:0
6:0
7
Bit
Bit
Bit
7
P1SKIP[6:0] Port 1 Crossbar Skip Enable Bits.
Unused
Name
Unused
P1[6:0]
Name
7
0
7
0
Unused.
Read =0b; Write = Don’t Care.
Port 1 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Unused.
Read =0b; Write = Don’t Care.
These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins used
for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
6
1
6
0
Description
5
1
5
0
Rev. 1.0
4
1
4
0
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
P1SKIP[6:0]
C8051F91x-C8051F90x
Function
P1[6:0]
R/W
R/W
Write
3
1
3
0
2
1
2
0
0: P1.n Port pin is logic
LOW.
1: P1.n Port pin is logic
HIGH.
1
1
1
0
Read
0
1
0
0
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