C8051F902-GM Silicon Laboratories Inc, C8051F902-GM Datasheet - Page 223

• Manufacturer Part Number: C8051F902-GM
• Description: IC MCU 8BIT 8KB FLASH 24QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F9xxr

Specifications of C8051F902-GM

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 24-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 15x10/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F9x
• Core: 8051
• Data Ram Size: 768 B
• Interface Type: UART
• Maximum Clock Frequency: 25 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F912DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Package: 24QFN EP
• Device Core: 8051
• Family Name: C8051F90x
• Maximum Speed: 25 MHz
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1848-5

SFR Definition 21.17. P1DRV: Port1 Drive Strength
SFR Page = 0xF; SFR Address = 0xA5
SFR Definition 21.18. P2: Port2
SFR Page = All Pages; SFR Address = 0xA0; Bit-Addressable
Name
Reset
Name
Reset
Type
Bit
6:0
Type
7
6:0
Bit
Bit
Bit
7
P1DRV[6:0]
Unused
Name
Unused
Name
R/W
P2
P2
7
0
7
1
Unused.
Read =0b; Write = Don’t Care.
Drive Strength Configuration Bits for
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P1.n Output has low output drive strength.
1: Corresponding P1.n Output has high output drive strength.
Port 2 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Unused.
Read = 0000000b; Write = Don’t Care.
6
0
6
0
Description
5
0
5
0
Rev. 1.0
4
0
4
0
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
C8051F91x-C8051F90x
P1.6–P1.0 (respectively).
P1DRV[6:0]
Function
R/W
Read
3
0
3
0
2
0
2
0
0: P2.7 Port pin is logic
LOW.
1: P2.7 Port pin is logic
HIGH.
1
0
1
0
Write
0
0
0
0
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