C8051F902-GM Silicon Laboratories Inc, C8051F902-GM Datasheet - Page 19

• Manufacturer Part Number: C8051F902-GM
• Description: IC MCU 8BIT 8KB FLASH 24QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F9xxr

Specifications of C8051F902-GM

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 24-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 15x10/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F9x
• Core: 8051
• Data Ram Size: 768 B
• Interface Type: UART
• Maximum Clock Frequency: 25 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F912DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Package: 24QFN EP
• Device Core: 8051
• Family Name: C8051F90x
• Maximum Speed: 25 MHz
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1848-5

C2CK/RST
C2CK/RST
VDD/DC+
VDD/DC+
GND/DC-
GND/DC-
XTAL3
XTAL4
XTAL3
XTAL4
DCEN
DCEN
VBAT
VBAT
GND
GND
Power Net
Power Net
Converter
Converter
Programming
Programming
C2D
Reset/PMU
C2D
DC/DC
Reset/PMU
DC/DC
Power On
Power On
Hardware
Analog
Hardware
Analog
Power
Power
Debug /
Debug /
XTAL1
XTAL2
XTAL1
XTAL2
Reset
Wake
Wake
Reset
VREG
VREG
SmaRTClock
Low Power
SmaRTClock
Low Power
24.5 MHz
Precision
Oscillator
Oscillator
Oscillator
24.5 MHz
Oscillator
Oscillator
Oscillator
External
Oscillator
Precision
20 MHz
External
Oscillator
Digital
Power
System Clock
20 MHz
Controller Core
Circuit
Configuration
Digital
Power
System Clock
Controller Core
Circuit
Configuration
8k Byte ISP Flash
Program Memory
Figure 1.3. C8051F902 Block Diagram
8k Byte ISP Flash
Figure 1.4. C8051F901 Block Diagram
CIP-51 8051
Program Memory
256 Byte SRAM
512 Byte XRAM
CIP-51 8051
256 Byte SRAM
512 Byte XRAM
SYSCLK
SYSCLK
Engine
Engine
CRC
CRC
SFR
Bus
SFR
Bus
Rev. 1.0
Internal
VREF
Internal
CP1, CP1A
Timers 0,
12/10-bit
75/300ksps
ADC
VREF
CP1, CP1A
Timers 0,
SMBus
SPI 0,1
UART
1, 2, 3
Analog Peripherals
6-bit
IREF
SPI 0,1
Digital Peripherals
PCA/
SMBus
WDT
6-bit
IREF
10-bit
300ksps
ADC
UART
1, 2, 3
Analog Peripherals
Port I/O Configuration
Digital Peripherals
PCA/
WDT
CP0, CP0A
C8051F91x-C8051F90x
Port I/O Configuration
CP0, CP0A
Crossbar Control
Crossbar Control
External
VREF
External
VREF
Comparators
Comparators
+
-
+
-
M
U
A
X
M
A
U
X
+
Crossbar
-
Decoder
+
-
Priority
Crossbar
Decoder
Priority
IREF0
Sensor
IREF0
VREF
Temp
GND
VDD
Sensor
VREF
Temp
VDD
GND
Drivers
Drivers
Drivers
Port 0
Port 1
Port 2
Drivers
Drivers
Drivers
Port 0
Port 1
Port 2
P0.0/VREF
P0.1/AGND
P0.2/XTAL1/RTCOUT
P0.3/XTAL2/WAKEOUT
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P2.7/C2D
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P2.7/C2D
19