C8051F902-GM Silicon Laboratories Inc, C8051F902-GM Datasheet - Page 172

• Manufacturer Part Number: C8051F902-GM
• Description: IC MCU 8BIT 8KB FLASH 24QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F9xxr

Specifications of C8051F902-GM

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 24-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 15x10/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F9x
• Core: 8051
• Data Ram Size: 768 B
• Interface Type: UART
• Maximum Clock Frequency: 25 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F912DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Package: 24QFN EP
• Device Core: 8051
• Family Name: C8051F90x
• Maximum Speed: 25 MHz
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1848-5

C8051F91x-C8051F90x
18.1. Power-On (VBAT Supply Monitor) Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
V
V
Figure 18.3 plots the power-on and V
power-on reset delay (T
3.6 V).
Note: The maximum V
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000), software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset.
On ‘F912 and ‘F902 devices, the VBAT supply monitor can be disabled to save power by writing ‘1’ to the
MONDIS (PMU0MD.5) bit. When the VBAT supply monitor is disabled, all reset sources will trigger a full
POR and will re-enable the VBAT supply monitor.
172
POR
BAT
See specification
table for min/max
voltages.
. An additional delay occurs before the device is released from reset; the delay decreases as the
ramp time increases (V
before V
BAT
Logic HIGH
Logic LOW
reaches the V
~0.8
~0.5
0.6
DD
PORDelay
ramp time is 3 ms; slower ramp times may cause the device to be released from reset
Figure 18.2. Power-Fail Reset Timing Diagram
RST
POR
BAT
) is typically 3 ms (V
level.
V
ramp time is defined as how fast V
POR
DD
monitor reset timing. For valid ramp times (less than 3 ms), the
Power-On
Reset
Rev. 1.0
T
PORDelay
BAT
= 0.9 V), 7 ms (V
Power-On
BAT
Reset
BAT
ramps from 0 V to V
= 1.8 V), or 15 ms (V
T
PORDelay
BAT
settles above
VBAT
BAT
POR
t
).
=