C8051F902-GM Silicon Laboratories Inc, C8051F902-GM Datasheet - Page 137

• Manufacturer Part Number: C8051F902-GM
• Description: IC MCU 8BIT 8KB FLASH 24QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F9xxr

Specifications of C8051F902-GM

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 24-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 15x10/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F9x
• Core: 8051
• Data Ram Size: 768 B
• Interface Type: UART
• Maximum Clock Frequency: 25 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F912DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Package: 24QFN EP
• Device Core: 8051
• Family Name: C8051F90x
• Maximum Speed: 25 MHz
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1848-5

13.5. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of VDD, system clock frequency, or temperature. This accidental execution of Flash
modifying code can result in alteration of Flash memory contents causing a system failure that is only
recoverable by re-Flashing the code in the device.
To help prevent the accidental modification of Flash by firmware, the VDD Monitor must be enabled and
enabled as a reset source on C8051F91x-C8051F90x devices for the Flash to be successfully modified. If
either the VDD Monitor or the VDD Monitor reset source is not enabled, a Flash Error Device Reset
will be generated when the firmware attempts to modify the Flash.
The following guidelines are recommended for any system that contains routines which write or erase
Flash from code.
13.5.1. VDD Maintenance and the VDD Monitor
Note: On C8051F91x-C8051F90x devices, both the VDD Monitor and the VDD Monitor reset
source must be enabled to write or erase Flash without generating a Flash Error Device Reset.
Note: On C8051F91x-C8051F90x devices, both the VDD Monitor and the VDD Monitor reset
source are enabled by hardware after a power-on reset.
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient
2. Make certain that the minimum VDD rise time specification of 1 ms is met. If the system can-
3. Keep the on-chip VDD Monitor enabled and enable the VDD Monitor as a reset source as
4. As an added precaution, explicitly enable the VDD Monitor and enable the VDD Monitor as a
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1. Areas
protection devices to the power supply to ensure that the supply voltages listed in the Absolute
Maximum Ratings table are not exceeded.
not meet this rise time specification, then add an external VDD brownout circuit to the RST pin
of the device that holds the device in reset until VDD reaches the minimum device operating
voltage and re-asserts RST if VDD drops below the minimum device operating voltage.
early in code as possible. This should be the first set of instructions executed after the Reset
Vector. For C-based systems, this will involve modifying the startup code added by the C com-
piler. See your compiler documentation for more details. Make certain that there are no delays
in software between enabling the VDD Monitor and enabling the VDD Monitor as a reset
source. Code examples showing this can be found in “AN201: Writing to Flash from Firm-
ware," available from the Silicon Laboratories website.
reset source inside the functions that write and erase Flash memory. The VDD Monitor enable
instructions should be placed just after the instruction to set PSWE to a 1, but before the Flash
write or erase operation instruction.
operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For exam-
ple, "RSTSRC = 0x02" is correct, but "RSTSRC |= 0x02" is incorrect.
to check are initialization code which enables other reset sources, such as the Missing Clock
Detector or Comparator, for example, and instructions which force a Software Reset. A global
search on "RSTSRC" can quickly verify this.
Rev. 1.0
C8051F91x-C8051F90x
137