AT91SAM7L64-AU Atmel, AT91SAM7L64-AU Datasheet - Page 501

• Manufacturer Part Number: AT91SAM7L64-AU
• Description: MCU ARM7 64K HS FLASH 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7L64-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 36MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.55 V ~ 1.8 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Controller Family/series: AT91SAM7xxx
• No. Of I/o's: 80
• Ram Memory Size: 6KB
• Cpu Speed: 36MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 6 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 36 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM7L-STK - KIT EVAL FOR AT91SAM7LAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

34.5.4
Figure 34-9. Memory Management
34.5.5
6257A–ATARM–20-Feb-08
COM0 time slot
COM1 time slot
COM2 time slot
SLCDC memory
Display Features
COM0
COM1
COM2
When a bit in the display memory (SLDC_MEM) is written to one, the corresponding segment is
energized (on), and non-energized when a bit in the display memory is written to zero.
At the beginning of each common, the display buffer is updated. The value of the previous com-
mon is latched in the display memory (it’s value is transferred from the user buffer to the frame
buffer).
The advantages of this solution are:
In order to improve the flexibility of SLCDC the following set of display modes are embedded:
• Ability to access the user buffer at any time in the frame, in any display mode and even in low
• Ability to change only one pixel without reloading the picture
1. Force Mode Off: All pixels are turned off and the memory content is kept.
2. Force Mode On: All pixels are turned on and the memory content is kept.
3. Inverted Mode: All pixels are set in the inverted state as defined in SLCDC memory and
4. Two Blinking Modes:
5. Buffer Swap Mode: All pixels are alternatively assigned to the state defined in the user
power waveform
loaded from the usr buff
Display data previously
the memory content is kept.
– Standard Blinking Mode: All pixels are alternately turned off to the predefined state
– Inverted Blinking Mode: All pixels are alternately turned off to the predefined
buffer then to the state defined in the display buffer.
to the disp buff
in SLCDC memory at LCDBLKFREQ frequency.
opposite state in SLCDC memory at LCDBLKFREQ frequency.
loaded from the usr buff
Display data previously
usr buff to the disp buff
Load data from the
to the disp buff
AT91SAM7L128/64 Preliminary
loaded from the usr buff
usr buff to the disp buff
Display data previously
Load data from the
to the disp reg
usr buff = user buffer
disp buf = display buffer
usr buff to the disp buff
Load data from the
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