AT91SAM7L64-AU Atmel, AT91SAM7L64-AU Datasheet - Page 150

• Manufacturer Part Number: AT91SAM7L64-AU
• Description: MCU ARM7 64K HS FLASH 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7L64-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 36MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.55 V ~ 1.8 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Controller Family/series: AT91SAM7xxx
• No. Of I/o's: 80
• Ram Memory Size: 6KB
• Cpu Speed: 36MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 6 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 36 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM7L-STK - KIT EVAL FOR AT91SAM7LAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19.3.3.5
150
AT91SAM7L128/64 Preliminary
GPNVM Bit
One error can be detected in the MC_FSR register after a programming sequence:
It is possible to clear lock bits previously set. Then the locked region can be erased or pro-
grammed. The unlock sequence is:
One error can be detected in the MC_FSR register after a programming sequence:
The status of lock bits can be returned by the Enhanced Embedded Flash Controller (EEFC).
The Get Lock Bit status sequence is:
For example, if the third bit of the first word read in the MC_FRR is set, then the third lock region
is locked.
One error can be detected in the MC_FSR register after a programming sequence:
Note:
GPNVM bits do not interfere with the embedded Flash memory plane. Refer to the product defi-
nition section for information on the GPNVM Bit Action.
The set GPNVM bit sequence is:
• When the locking completes, the bit FRDY in the Flash Programming Status Register
• If the lock bit number is greater than the total number of lock bits, then the command has no
• a Command Error: a bad keyword has been written in the MC_FCR register.
• The Clear Lock command (CLB) and a page number to be unprotected are written in the
• When the unlock completes, the bit FRDY in the Flash Programming Status Register
• If the lock bit number is greater than the total number of lock bits, then the command has no
• a Command Error: a bad keyword has been written in the MC_FCR register.
• The Get Lock Bit command (GLB) is written in the Flash Command Register. FARG field is
• When the command completes, the bit FRDY in the Flash Programming Status Register
• Lock bits can be read by the software application in the MC_FRR register. The first word read
• a Command Error: a bad keyword has been written in the MC_FCR register.
• Start the Set GPNVM Bit command (SGPB) by writing the Flash Command Register with the
(MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the
interrupt line of the Memory Controller is activated.
effect. The result of the SLB command can be checked running a GLB (Get Lock Bit)
command.
Flash Command Register.
(MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the
interrupt line of the Memory Controller is activated.
effect.
meaningless.
(MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the
interrupt line of the Memory Controller is activated.
corresponds to the 32 first lock bits, next reads providing the next 32 lock bits as long as it is
meaningful. Extra reads to the MC_FRR register return 0.
SGPB command and the number of the GPNVM bit to be set.
Access to the Flash in read is permitted when a set, clear or get lock bit command is performed.
6257A–ATARM–20-Feb-08