AT91SAM7L64-AU Atmel, AT91SAM7L64-AU Datasheet - Page 169
![MCU ARM7 64K HS FLASH 128-LQFP](/photos/6/71/67112/128-lqfp_sml.jpg)
AT91SAM7L64-AU
Manufacturer Part Number
AT91SAM7L64-AU
Description
MCU ARM7 64K HS FLASH 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7L64-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
36MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.55 V ~ 1.8 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Controller Family/series
AT91SAM7xxx
No. Of I/o's
80
Ram Memory Size
6KB
Cpu Speed
36MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
6 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
36 MHz
Number Of Programmable I/os
80
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
For Use With
AT91SAM7L-STK - KIT EVAL FOR AT91SAM7LAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (9Mb)
20.3.4
20.3.4.1
20.3.4.2
6257A–ATARM–20-Feb-08
Device Operations
Flash Read Command
Flash Write Command
The write handshake is done by polling the Debug Comms Control Register until the R bit is
cleared. Once cleared, data can be written to the Debug Comms Data Register.
The read handshake is done by polling the Debug Comms Control Register until the W bit is set.
Once set, data can be read in the Debug Comms Data Register.
Several commands on the Flash memory are available. These commands are summarized in
Table 20-3 on page
is reading and writing the Debug Comms Registers.
This command is used to read the Flash contents. The memory map is accessible through this
command. Memory is seen as an array of words (32-bit wide). The read command can start at
any valid address in the memory plane. This address must be word-aligned. The address is
automatically incremented.
Table 20-18. Read Command
This command is used to write the Flash contents. The address transmitted must be a valid
Flash address in the memory plane.
The Flash memory plane is organized into several pages. Data to be written is stored in a load
buffer that corresponds to a Flash memory page. The load buffer is automatically flushed to the
Flash:
The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be
chained; an internal address buffer is automatically increased.
Table 20-19. Write Command
Read/Write
Write
Write
Read
Read
...
Read
Read/Write
Write
Write
Write
• before access to any page than the current one
• at the end of the number of words transmitted
– Bit 0 (R): Denotes whether the programmer can send data from the Debug Comms
Data Register. If R = 1, data previously placed there through the scan chain has not
been collected by the device and so the programmer must wait.
159. Commands are run by the programmer through the serial interface that
DR Data
(Number of Words to Read) << 16 | READ
Address
Memory [address]
Memory [address+4]
...
Memory [address+(Number of Words to Read - 1)* 4]
DR Data
(Number of Words to Write) << 16 | (WP or WPL or EWP or EWPL)
Address
Memory [address]
AT91SAM7L128/64 Preliminary
169
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