AT91SAM7L64-AU Atmel, AT91SAM7L64-AU Datasheet - Page 110

• Manufacturer Part Number: AT91SAM7L64-AU
• Description: MCU ARM7 64K HS FLASH 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7L64-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 36MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.55 V ~ 1.8 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Controller Family/series: AT91SAM7xxx
• No. Of I/o's: 80
• Ram Memory Size: 6KB
• Cpu Speed: 36MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 6 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 36 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM7L-STK - KIT EVAL FOR AT91SAM7LAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

17.3.6
17.3.6.1
110
AT91SAM7L128/64 Preliminary
Power Supply Control
Controlling the Backup Power Supply
Until vr_ok is deactivated, the vddcore_nreset signal remains active.
The backup power supply can be controlled by the main power switch. This main power switch
can only be enabled by tying the FWUP pin to GND. As soon as the power has risen, the Supply
Controller maintains the main power switch closed by asserting the signal, supply_on.
The main power switch can be opened by the software by writing the Supply Controller Control
Register SUPC_CR with the shutdown bit, SHDW set at 1.
Writing SUPC_CR with SHDW set at 1 results in the following actions:
The shutdown sequence led by writing SHDW is described in
It is also possible to wait the current frame of the LCD Controller before shutting down the LCD
Controller power supply. This can be done by writing the SHDWEOF bit to 1, instead of the
SHDW bit.
If SHDWEOF is set, the sequence is exactly the same, except the end_of_frame signal shall be
asserted for at least one slow clock cycle before the lcd_nreset signal is asserted and the charge
pump is disabled.
The shutdown sequence led by writing SHDWEOF is described in
• asserts the vddcore_nreset signal then switches off the voltage regulator
• if the LCD charge pump is enabled, asserts the lcd_nreset signal then disables the LCD
• asserts the Flash Memory reset signal and disables the Flash Memory power supply
• disables the SRAM power supply
• asserts the Clock reset signal, rt_nreset, then disables the Clock power supply
• releases the supply_on signal, thus switching off the backup power supply and enters Off
charge pump
Mode.
Figure 17-6 on page
Figure 17-7 on page
6257A–ATARM–20-Feb-08
111.
112.