AT91SAM7L64-AU Atmel, AT91SAM7L64-AU Datasheet - Page 133

• Manufacturer Part Number: AT91SAM7L64-AU
• Description: MCU ARM7 64K HS FLASH 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7L64-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 36MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.55 V ~ 1.8 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Controller Family/series: AT91SAM7xxx
• No. Of I/o's: 80
• Ram Memory Size: 6KB
• Cpu Speed: 36MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 6 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 36 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM7L-STK - KIT EVAL FOR AT91SAM7LAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.3.2.1
18.3.2.2
6257A–ATARM–20-Feb-08
Internal Memory Mapping
Internal Memory Area 0
Within the Internal Memory address space, the Address Decoder of the Memory Controller
decodes eight more address bits to allocate 1-Mbyte address spaces for the embedded
memories.
The allocated memories are accessed all along the 1-Mbyte address space and so are repeated
n times within this address space, n equaling 1 Mbyte divided by the size of the memory.
When the address of the access is undefined within the internal memory area, the Address
Decoder returns an Abort to the master.
The first 32 bytes of Internal Memory Area 0 contain the ARM processor exception vectors, in
particular, the Reset Vector at address 0x0.
Before execution of the remap command, the ROM or Flash is mapped into Internal Memory
Area 0, depending on the GPNVM Bit 0 state. After the remap command, the 4Kb internal core
SRAM at address 0x0020 0000 is mapped into Internal Memory Area 0. The memory mapped
into Internal Memory Area 0 is accessible in both its original location and at address 0x0. The
user can see the 6 Kbytes contiguously at address 0x002F F000.
Figure 18-3
GPNVM Bit 0 state.
Figure 18-3. Internal Memory Mapping with GPNVM Bit 0 = 0
256 Mbytes
and
Figure 18-4
0x0000 0000
0x0010 0000
0x0020 0000
0x0030 0000
0x0040 0000
0x000F FFFF
0x001F FFFF
0x002F FFFF
0x003F FFFF
0x0FFF FFFF
0x004F FFFF
0x0050 0000
illustrate the Internal memory mapping in accrodance to the
Core SRAM (4 Kbytes) After Remap
AT91SAM7L128/64 Preliminary
Internal SRAM (Backup)
Internal SRAM (Core)
ROM Before Remap
Undefined Areas
Internal FLASH
Internal ROM
12 Kbytes
4 Kbytes
2 Kbytes
(Abort)
1 Mbyte
1 Mbyte
1 Mbyte
1 Mbyte
1 Mbyte
251 Mbytes
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