AT91SAM7L64-AU Atmel, AT91SAM7L64-AU Datasheet - Page 167
![MCU ARM7 64K HS FLASH 128-LQFP](/photos/6/71/67112/128-lqfp_sml.jpg)
AT91SAM7L64-AU
Manufacturer Part Number
AT91SAM7L64-AU
Description
MCU ARM7 64K HS FLASH 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7L64-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
36MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.55 V ~ 1.8 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Controller Family/series
AT91SAM7xxx
No. Of I/o's
80
Ram Memory Size
6KB
Cpu Speed
36MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
6 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
36 MHz
Number Of Programmable I/os
80
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
For Use With
AT91SAM7L-STK - KIT EVAL FOR AT91SAM7LAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Table 20-16. Signal Description List (Continued)
Note:
20.3.2
6257A–ATARM–20-Feb-08
Signal Name
TCK
TDI
TDO
TMS
1. See
Entering Serial Programming Mode
Figure 20-6
Function
JTAG TCK
JTAG Test Data In
JTAG Test Data Out
JTAG Test Mode Select
below.
Figure 20-6. The Charge Pump and the LCD Regulator are Not Used
The following algorithm puts the device in Serial Programming Mode:
Note:
• Apply GND, TST, CLKIN, FWUP and the supplies as described in
• Apply XIN clock.
• Wait for 10 ms.
• Reset the TAP controller clocking 5 TCK pulses with TMS set.
• Shift 0x2 into the IR register (IR is 4 bits long, LSB first) without going through the Run-Test-
• Shift 0x2 into the DR register (DR is 4 bits long, LSB first) without going through the Run-
• Shift 0xC into the IR register (IR is 4 bits long, LSB first) without going through the Run-Test-
Description List,” on page
Idle state.
Test-Idle state.
Idle state.
After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an
external clock ( > 32 kHz) is connected to XIN, then the device will switch on the external clock.
Else, XIN input is not considered. An higher frequency on XIN speeds up the programmer
handshake.
External supply
158.
JTAG
VDDINLCD
VDDLCD
VDD3V6
VDDIO2
AT91SAM7L128/64 Preliminary
Output
Type
Input
Input
Input
Active
Level
Regulator
-
-
-
-
Voltage
Charge
Pump
LCD
Pulled-up input at reset
Pulled-up input at reset
Comments
Pulled-up input at reset
Table 20-1, “Signal
CAPP1
CAPM1
CAPP2
CAPM2
167
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