AT91SAM7L64-AU Atmel, AT91SAM7L64-AU Datasheet - Page 247

• Manufacturer Part Number: AT91SAM7L64-AU
• Description: MCU ARM7 64K HS FLASH 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7L64-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 36MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.55 V ~ 1.8 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Controller Family/series: AT91SAM7xxx
• No. Of I/o's: 80
• Ram Memory Size: 6KB
• Cpu Speed: 36MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 6 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 36 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM7L-STK - KIT EVAL FOR AT91SAM7LAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 26-4. Start Bit Detection
Figure 26-5. Character Reception
26.4.2.3
Figure 26-6. Receiver Ready
26.4.2.4
Figure 26-7. Receiver Overrun
26.4.2.5
6257A–ATARM–20-Feb-08
Receiver Ready
Receiver Overrun
Parity Error
Example: 8-bit, parity enabled 1 stop
Sampling
RXRDY
Sampling Clock
RXRDY
OVRE
DRXD
DRXD
DRXD
Baud Rate
DRXD
Clock
S
S
When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY sta-
tus bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the
receive holding register DBGU_RHR is read.
If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the
last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in
DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR with
the bit RSTSTA (Reset Status) at 1.
Each time a character is received, the receiver calculates the parity of the received data bits, in
accordance with the field PAR in DBGU_MR. It then compares the result with the received parity
0.5 bit
period
D0
D0
True Start Detection
D1
D1
period
D2
1 bit
D2
D3
D0
D3
D4
D4
D1
D5
D5
D6
D6
True Start
Detection
D2
D7
D7
P
P
D3
stop
AT91SAM7L128/64 Preliminary
S
S
D4
Read DBGU_RHR
D0
D0
D1
D1
D5
D2
D2
D3
D3
D6
D4
D4
D5
D5
D7
D6
D6
Parity Bit
D7
D7
P
P
stop
Stop Bit
D0
RSTSTA
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