AT91SAM7L64-AU Atmel, AT91SAM7L64-AU Datasheet
AT91SAM7L64-AU
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AT91SAM7L64-AU Summary of contents
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... Internal High-speed Flash – 128 Kbytes (AT91SAM7L128), Organized in 512 Pages of 256 Bytes Single Plane – 64 Kbytes (AT91SAM7L64), Organized In 256 Pages of 256 Bytes Single Plane – Single Cycle Access MHz in Worst Case Conditions – 128-bit Read Access – Page Programming Time: 4.6 ms, Including Page Auto Erase, Full Erase Time – ...
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... Double PWM Generation, Capture/Waveform Mode, Up/Down Capability • One Four-channel 16-bit PWM Controller (PWMC) • One Two-wire Interface (TWI) – Master, Multi-Master and Slave Mode Support, All Atmel – General Call Supported in Slave Mode • One 4-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os ® ...
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... ARM7 • AT91SAM7L128 features a 128 Kbyte high-speed Flash and a total of 6 Kbytes SRAM. • AT91SAM7L64 features a 64 Kbyte high-speed Flash and a total of 6 Kbytes SRAM. They also embed a large set of peripherals, including a Segment LCD Controller and a complete set of system functions minimizing the number of external components. ...
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Block Diagram Figure 2-1. AT91SAM7L128/64 Block Diagram TDI TDO TMS TCK JTAGSEL TST FIQ IRQ0-IRQ1 PCK0-PCK2 CLKIN PLL PLLRC XIN OSC XOUT 32k RCOSC VDDIO1 BOD POR VDDIO1 NRST NRSTB FWUP VDDIO1 DRXD DTXD SEG00-SEG39 COM0-COM9 RXD0 TXD0 SCK0 ...
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Signal Description Table 3-1. Signal Description List Signal Name Function I/O Lines (PIOC) and Voltage Regulator VDDIO1 Power Supply VDDOUT Voltage Regulator Output VDDCORE Core Power Supply VDDINLCD Charge Pump Power Supply VDD3V6 Charge Pump Output VDDLCD LCD Voltage ...
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Table 3-1. Signal Description List (Continued) Signal Name Function NRST Microcontroller Reset TST Test Mode Select NRSTB Asynchronous Master Reset DRXD Debug Receive Data DTXD Debug Transmit Data IRQ0 - IRQ1 External Interrupt Inputs FIQ Fast Interrupt Input PA0 - ...
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Table 3-1. Signal Description List (Continued) Signal Name Function TWD Two-wire Serial Data TWCK Two-wire Serial Clock AD0-AD3 Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference PGMEN0- Programming Enabling PGMEN2 PGMM0- Programming Mode PGMM3 PGMD0- Programming Data PGMD15 PGMRDY Programming ...
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Package and Pinout The AT91SAM7L128/64 is available in: • 128-lead LQFP package with a 0.5 mm lead-pitch • 144-ball LFBGA package with a 0.8 mm pitch. The part is also available ...
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LQFP Package Pinout Table 4-1. Pinout for 128-lead LQFP Package 1 TST 33 2 VDDCORE 34 3 PA0 35 4 PA1 36 5 PA2 37 6 PA3 38 7 PA4 39 8 PA5 40 9 PA6 41 10 ...
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LFBGA Package Outline Figure 4-2 A detailed mechanical description is given in the Mechanical Characteristics section of the prod- uct datasheet. Figure 4-2. AT91SAM7L128/64 Preliminary 10 shows the orientation of the 144-ball LFBGA package. 144-ball LFBGA Package Outline ...
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LFBGA Pinout Table 4-2. SAM7L128/64 Pinout for 144-ball LFBGA Package Pin Signal Name Pin A1 XOUT D1 A2 XIN D2 A3 VDDCORE D3 A4 GND D4 A5 PLLRCGND D5 A6 PLLRC D6 A7 PC24/PGMD13 D7 A8 PC23//PGMD12 D8 ...
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Power Considerations 5.1 Power Supplies The AT91SAM7L128/64 has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: • VDDOUT pin. ...
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Table 5-1 on page 13 When entering this mode, all PIO pins keep their previous states, they are reinitialized as inputs with pull-ups at wake-up. The AT91SAM7L128/64 can be awakened from this mode through the FWUP pin, an event on ...
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Wake-up Sources The wake-up events allow the device to exit from backup mode. When a wake-up event is detected, the supply controller performs a sequence which automatically reenables the voltage regulator and the backup SRAM power supply ...
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Figure 5-2. 5.5 Voltage Regulator The AT91SAM7L128/64 embeds a voltage regulator that is managed by the supply controller. This internal regulator is only intended to supply the internal core of AT91SAM7L128/64. It fea- tures three different operating modes: • In ...
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Adequate input supply decoupling is mandatory for VDDIO1 in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel, 100 ...
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Figure 5-4. If the charge pump is not needed, the user can apply an external voltage. See Figure 5-5. Please note that in this topology, switching time enhancement buffers are not available. (Refer Section 10.13 ”Segment LCD 6257AS–ATARM–28-Feb-08 AT91SAM7L128/64 Preliminary ...
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Typical Powering Schematics The AT91SAM7L128/64 supports a 1.8V-3.6V single supply mode. The internal regulator input connected to the source and its output feeds VDDCORE. ics to be used. Figure 5-6. AT91SAM7L128/64 Preliminary 18 3.3V System Single Power Supply Schematic ...
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I/O Line Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven VDDIO, and has no pull-up resistor. ...
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PIO Controller Lines All the I/O lines; PA0 to PA25, PB0 to PB23, PC0 to PC29 integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO controllers. All I/Os ...
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Processor and Architecture 7.1 ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann Architecture – Runs MHz, providing 0.9 MIPS/MHz • Two instruction sets – ARM – Thumb high code density 16-bit instruction set ...
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Embedded Flash interface three programmable wait states – Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required – Key-protected program, erase and lock/unlock sequencer – Single command for erasing, programming and locking operations – Interrupt ...
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... Protection Mode to secure contents of the Flash • 64 Kbytes of Flash Memory (AT91SAM7L64) – Single plane – One bank of 256 pages of 256 bytes – Fast access time, 15 MHz single-cycle access in Worst Case conditions – ...
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Figure 8-1. Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256 MBytes 0x0FFF FFFF 0x1000 0000 Undefined 14 x 256 MBytes (Abort) 3,584 MBytes 0xEFFF FFFF 0xF000 0000 Internal Peripherals 256M Bytes 0xFFFF FFFF AT91SAM7L128/64 Preliminary 24 Internal Memory ...
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... Internal Flash • The AT91SAM7L128 features one bank of 128 Kbytes of Flash. • The AT91SAM7L64 features one bank of 64 Kbytes of Flash. At any time, the Flash is mapped to address 0x0010 0000. A general purpose NVM (GPNVM1) bit is used to boot either on the ROM (default) or from the Flash. This GPNVM1 bit can be cleared or set respectively through the commands “ ...
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... Flash Overview • The Flash of the AT91SAM7L128 is organized in 512 pages (single plane) of 256 bytes. • The Flash of the AT91SAM7L64 is organized in 256 pages (single plane) of 256 bytes. The Flash contains a 128-byte write buffer, accessible through a 32-bit interface. 8.1.2.2 Flash Power Supply The Flash is supplied by VDDCORE through a power switch controlled by the Supply Controller ...
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... Each lock region has a size of 8 Kbytes. The AT91SAM7L64 Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7L64 con- tains 8 lock regions and each lock region contains 32 pages of 256 bytes. Each lock region has a size of 8 Kbytes locked-region’ ...
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... TST and CLKIN are tied high while FWUP is tied low. • The Flash of the AT91SAM7L128 is organized in 512 pages of 256 bytes (single plane). • The Flash of the AT91SAM7L64 is organized in 256 pages of 256 bytes (single plane). The Flash contains a 128-byte write buffer, accessible through a 32-bit interface. ...
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System Controller The System Controller manages all vital blocks of the microcontroller, interrupts, clocks, power, time, debug and reset. The System Controller Block Diagram is shown in 9.1 System Controller Mapping The System Controller peripherals are all mapped to ...
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Figure 9-1. System Controller Block Diagram FWUP NRSTB Zero-Power Power-on Reset Brownout Detector WKUP0 - WKUP15 SLCK XIN Xtal 32 kHz Oscillator XOUT Embedded 32 kHz RC Oscillator Backup Power Supply core_nreset NRST FSTT0 - FSTT15 Embedded 2 MHz RC ...
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Supply Controller (SUPC) The Supply Controller controls the power supplies of each section of the product: • the processor and the peripherals • the Flash memory • the backup SRAM • the LCD controller, the charge pump and the ...
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BOD current consumption is 25 µA, typically. To decrease current consumption, the software can disable the brownout detector, especially in low-power mode. The software can also configure the BOD in “switched” mode. In this mode, an internal state machine switches ...
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Figure 9-2. 9.5 Power Management Controller The Power Management Controller uses the clock generator outputs to provide: • The Processor Clock PCK • The Master Clock MCK • All the peripheral clocks, independently controllable • Three programmable clock outputs PCKx ...
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Figure 9-3. 9.6 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ ARM Processor • Individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is ...
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... Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of – Chip ID is 0x2733 0740 (VERSION 0) for AT91SAM7L128 – Chip ID is 0x2733 0540 (VERSION 0) for AT91SAM7L64 9.8 Period Interval Timer • 20-bit programmable counter plus 12-bit interval counter 9 ...
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Peripherals 10.1 User Interface The User Peripherals are mapped in the 256 MBytes of the address space between 0xF000 0000 and 0xFFFF EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in ...
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Peripheral Multiplexing on PIO Lines The AT91SAM7L128/64 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set. PIO Controller A, B and C control respectively 26, 24 and 30 lines. Each line ...
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PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 ...
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PIO Controller B Multiplexing Table 10-3. Multiplexing on PIO Controller B I/O Line Peripheral A PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 NPCS3 PB13 NPCS2 PB14 NPCS1 PB15 RTS1 PB16 RTS0 PB17 DTR1 ...
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PIO Controller C Multiplexing Table 10-4. Multiplexing on PIO Controller C I/O Line Peripheral A PC0 CTS1 PC1 DCD1 PC2 DTR1 PC3 DSR1 PC4 RI1 PC5 IRQ1 PC6 NPCS1 PC7 PWM0 PC8 PWM1 PC9 PWM2 PC10 TWD PC11 TWCK ...
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... Maximum frequency Master Clock 10.8 Two Wire Interface • Master, Multi-Master and Slave Mode Operation • Compatibility with Atmel two-wire interface, serial memory and I • One, two or three bytes for slave address • Sequential read/write operations • Bit Rate 400 kbit/s • ...
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Multi-drop Mode with address generation and detection – Optional Manchester Encoding • RS485 with driver control signal • ISO7816 Protocols for interfacing with smart cards – NACK handling, error counter with repetition ...
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Independent channel programming – Independent enable/disable commands – Independent clock selection – Independent period and duty cycle, with double buffering – Programmable selection of the output waveform polarity – Programmable center or left aligned output waveform 10.12 Analog-to-Digital Converter ...
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Package Drawings Figure 11-1. 128-lead LQFP Package Drawing . Table 11-1. AT91SAM7L128/64 Table 11-2. JEDEC Drawing Reference JESD97 Classification Table 11-3. Moisture Sensitivity Level AT91SAM7L128/64 Preliminary 44 Device and LQFP Package Maximum Weight 800 Package Reference MS-026 e3 LQFP ...
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Figure 11-2. 144-lead LFBGA Package Drawing All dimensions are in mm Table 11-4. AT91SAM7L128/64 Table 11-5. JEDEC Drawing Reference JESD97 Classification Table 11-6. Moisture Sensitivity Level This package respects the recommendations of the NEMI User Group. 6257AS–ATARM–28-Feb-08 AT91SAM7L128/64 Preliminary Device ...
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... Ordering Information Table 12-1. Ordering Information Ordering Code AT91SAM7L128-AU AT91SAM7L64-AU AT91SAM7L128-CU AT91SAM7L64-CU AT91SAM7L128/64 Preliminary 46 Package Package Type LQFP128 Green LQFP128 Green LFBGA144 Green LFBGA144 Green Temperature Operating Range Industrial (-40°C to 85°C) Industrial (-40°C to 85°C) Industrial (-40°C to 85°C) Industrial (-40°C to 85°C) ...
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Revision History Doc. Rev Comments 6257AS First issue 6257AS–ATARM–28-Feb-08 AT91SAM7L128/64 Preliminary Change Request Ref. 47 ...
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