AT91SAM7L64-AU Atmel, AT91SAM7L64-AU Datasheet - Page 113

• Manufacturer Part Number: AT91SAM7L64-AU
• Description: MCU ARM7 64K HS FLASH 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7L64-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 36MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.55 V ~ 1.8 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Controller Family/series: AT91SAM7xxx
• No. Of I/o's: 80
• Ram Memory Size: 6KB
• Cpu Speed: 36MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 6 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 36 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM7L-STK - KIT EVAL FOR AT91SAM7LAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

17.3.6.3
17.3.6.4
17.3.6.5
6257A–ATARM–20-Feb-08
Controlling the SRAM Power Supply
Controlling the Clock Alarm Power Supply
Controlling the LCD Voltage Regulator Power Supply
case, 2 slow clock cycles. Once the vddcore_nreset signal is asserted, the processor and the
peripherals are stopped 1 slow clock cycle before the core power supply becomes off.
The loss of voltage regulation while the core power supply is enabled can be programmed to
generate a reset by writing the VRRSTEN bit to 1 in the Supply Controller Mode Register,
SUPC_MR.
The Supply Controller can be used to switch on or off the power supply of the backup SRAM by
opening or closing the SRAM power switch. This power switch is controlled by the SRAMON bit
of the Supply Controller Mode Register, SUPC_MR. However, the battery backup SRAM is auto-
matically switched on when the core power supply is enabled, as the processor requires the
SRAM as data memory space (Please refer to
The Supply Monitor can be used to switch on or off the power supply of the Clock Alarm (Real
Time Clock (RTC)) by opening or closing the corresponding power switch. This power switch is
controlled by the RTON bit in SUPC_MR. After a backup reset, the Clock is not supplied (RTON
= 0).
The status of the Clock Power supply can be seen through the status register (RTS in SUPC_
SR).
There are several restrictions concerning the write of the RTON field:
The Supply Controller can be used to select the power supply source of the LCD voltage regula-
tor. The LCD voltage regulator can either be supplied through an external power supply or by the
embedded charge pump.
This selection is done by the LCDMODE field in the SUPC_MR register. After a backup reset,
the LCDMODE field is at 0x0, it means that no power supply source is selected and the LCD
Controller reset signal, lcd_nreset is asserted.
• If SRAMON is written to 1, there is no immediate effect, but the SRAM will be left powered
• If SRAMON is written to 0, there is no immediate effect, but the SRAM will be switched off
• If RTON is written to 1 while it is at 0, after the write resynchronization time (about 2 slow
• If RTON is written to 0 while it is at 1, after the write resynchronization time (about 2 slow
• The user must check that the previous power supply switch operation is done before writing
• Writing RTON at 1 while it is already at 1 or writing RTON at 0 while it is already at 0 is
when the Supply Controller enters backup mode, thus retaining its content.
when the Supply Controller enters backup mode. The SRAM is automatically switched on at
the exit of the backup mode.
clock cycles), the Clock power switch is closed by setting the signal, rt_on at 1, then after one
slow clock cycle, the rt_nreset signal is released. This ensures that the Clock is always
properly cleared when its power rises.
clock cycles), the rt_nreset signal is asserted, then after one slow clock cycle, the Clock
power switch is opened by resetting the signal, rt_on at 0.
RTON again. To do that, the user must check that the RTS flag has the correct value. If RTON
is written to 0, the RTS flag is reset at 0. If RTON is written to 1, the RTS flag is set at 1.
forbidden and has no effect.
AT91SAM7L128/64 Preliminary
Figure 17-2 on page
107).
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