AT91SAM7L64-AU Atmel, AT91SAM7L64-AU Datasheet - Page 17

• Manufacturer Part Number: AT91SAM7L64-AU
• Description: MCU ARM7 64K HS FLASH 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7L64-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 36MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.55 V ~ 1.8 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Controller Family/series: AT91SAM7xxx
• No. Of I/o's: 80
• Ram Memory Size: 6KB
• Cpu Speed: 36MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 6 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 36 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM7L-STK - KIT EVAL FOR AT91SAM7LAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

6257A–ATARM–20-Feb-08
Figure 5-4.
If the charge pump is not needed, the user can apply an external voltage. See
Figure 5-5.
Please note that in this topology, switching time enhancement buffers are not available. (Refer
Section 10.13 ”Segment LCD
External supply
External supply
The LCD Regulator is Externally Supplied
The Charge Pump and the LCD Regulator are Not Used
R = 10
Controller”.)
VDDINLCD
VDDINLCD
VDDLCD
VDDLCD
VDD3V6
VDD3V6
VDDIO2
VDDIO2
AT91SAM7L128/64 Preliminary
Regulator
Regulator
Voltage
Voltage
Charge
Charge
Pump
Pump
LCD
LCD
CAPP1
CAPM1
CAPP2
CAPM2
CAPP1
CAPM1
CAPP2
CAPM2
Figure 5-5
below:
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